ARITHMETIC UNIT, ARITHMETIC METHOD, AND PROGRAM

To improve an arithmetic performance of an inverse matrix without increasing the number of product-sum operator or a data bit width of a memory.SOLUTION: An arithmetic unit includes storage means that stores elements of a first matrix consisting of a coefficient matrix which is a symmetric matrix or...

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1. Verfasser: NAKAYAMA TADAYOSHI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To improve an arithmetic performance of an inverse matrix without increasing the number of product-sum operator or a data bit width of a memory.SOLUTION: An arithmetic unit includes storage means that stores elements of a first matrix consisting of a coefficient matrix which is a symmetric matrix or a Hermitian matrix and a unit matrix having the same size as the coefficient matrix, arranged left to right, and arithmetic means that calculates an inverse matrix of the coefficient matrix by performing an operation to eliminate columns in the coefficient matrix to zero based on the first matrix stored in the storage means. The arithmetic means performs a product-sum operation performed when eliminating the columns to zero with respect to only three regions of one triangular region in a first symmetric matrix on the coefficient matrix side of the first matrix, one triangular region in a second symmetric matrix on the unit matrix side of the first matrix, and one rectangular region in two rectangular regions excluding the first symmetric matrix and the second symmetric matrix from a square matrix encompassing the first symmetric matrix and the second symmetric matrix.SELECTED DRAWING: Figure 11 【課題】積和演算器の数やメモリのデータビット幅を増やすことなく、逆行列の演算性能を向上させる。【解決手段】演算装置は、対称行列又はエルミート行列である係数行列と、前記係数行列と同じサイズの単位行列とを、左右に配した第1行列の要素を格納する格納手段と、前記格納手段に格納された前記第1行列の要素に基づいて、前記係数行列における列をゼロ消去する演算を行い、前記係数行列の逆行列を計算する演算手段とを有し、前記演算手段は、前記列をゼロ消去する際に行う積和演算を、前記第1行列の前記係数行列側の第1対称行列における一方の三角領域と、前記第1行列の前記単位行列側の第2対称行列における一方の三角領域と、前記第1対称行列及び前記第2対称行列を包含する正方行列から前記第1対称行列及び前記第2対称行列を除いた2つの矩形領域の一方の矩形領域との3つの領域のみに関して行う。【選択図】図11