TEST NAND DEVICE AND NAND DEVICE DEBUGGING METHOD
To provide a test NAND device that can reproduce a defect in a short time.SOLUTION: A test NAND device includes: pseudo error generation instruction means 21 that instructs the test NAND device to generate a pseudo error; error content/range designation means 22 that designates contents and a range...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng ; jpn |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | To provide a test NAND device that can reproduce a defect in a short time.SOLUTION: A test NAND device includes: pseudo error generation instruction means 21 that instructs the test NAND device to generate a pseudo error; error content/range designation means 22 that designates contents and a range of the pseudo error to be generated; and pseudo error generation execution means 23 that generates and executes, when the pseudo error generation instructing means 21 instructs the generation of the pseudo error, and the error content/range designation means 22 designates the contents and the range of the pseudo error to be generated, a pseudo error according to the contents and the range of the instruction.SELECTED DRAWING: Figure 8
【課題】不具合の再現を短時間で行うことができるテスト用ＮＡＮＤ装置を提供する。【解決手段】テスト用ＮＡＮＤ装置に疑似エラーの発生を指示する疑似エラー発生指示手段２１と、発生する前記疑似エラーの内容と範囲を指定するエラー内容・範囲指定手段２２と、前記疑似エラー発生指示手段２１により疑似エラーの発生指示がなされ、前記エラー内容・範囲指定手段２２により発生する疑似エラーの内容と範囲の指定があると、この指示の内容と範囲に応じた疑似エラーを発生実行する疑似エラー発生実行手段２３と、を具備する。【選択図】図８ |
|---|