SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To provide a semiconductor device capable of suppressing variation in gate threshold voltage, in a structure with a contact trench.SOLUTION: A semiconductor device comprises: a semiconductor substrate 10 of a first conductivity type; an insulated gate electrode structure (6, 7) buried in a first tre...

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Hauptverfasser: KONO RYOICHI, KUBOUCHI MOTOYOSHI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a semiconductor device capable of suppressing variation in gate threshold voltage, in a structure with a contact trench.SOLUTION: A semiconductor device comprises: a semiconductor substrate 10 of a first conductivity type; an insulated gate electrode structure (6, 7) buried in a first trench 11 provided on the semiconductor substrate 10; a base region 3 of a second conductivity type provided on the semiconductor substrate 10 so as to be in contact with the first trench 11; a first main electrode region 4a, 4b of the first conductivity type provided above the base region 3 so as to be in contact with the first trench 11; a polysilicon film 15 of the second conductivity type buried in a second trench 14 provided on the semiconductor substrate 10, being in contact with the base region 3 and having a higher impurity concentration than the base region 3; and a second main electrode region 9 provided at a lower surface side of the semiconductor substrate 10.SELECTED DRAWING: Figure 2 【課題】コンタクトトレンチを有する構造において、ゲート閾値電圧のばらつきを抑制することができる半導体装置を提供する。【解決手段】第1導電型の半導体基板10と、半導体基板10に設けられた第1トレンチ11に埋め込まれた絶縁ゲート型電極構造(6,7)と、半導体基板10に第1トレンチ11に接して設けられた第2導電型のベース領域3と、ベース領域3の上部に第1トレンチ11に接して設けられた第1導電型の第1主電極領域4a,4bと、半導体基板10に設けられた第2トレンチ14に埋め込まれ、ベース領域3に接し、ベース領域3よりも高不純物濃度の第2導電型のポリシリコン膜15と、半導体基板10の下面側に設けられた第2主電極領域9を備える。【選択図】図2