SEMICONDUCTOR STORAGE DEVICE

To provide a semiconductor storage device capable of improving a cell integration degree.SOLUTION: A semiconductor storage device comprises: an integrated wire SI including a first wiring layer SGD3 including a first region SU3 and a second region SU2, which is disposed in parallel with the first re...

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Hauptverfasser: SUDA KEISUKE, DATE KOHEI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a semiconductor storage device capable of improving a cell integration degree.SOLUTION: A semiconductor storage device comprises: an integrated wire SI including a first wiring layer SGD3 including a first region SU3 and a second region SU2, which is disposed in parallel with the first region in a first direction Y, and a second wiring layer SGD2 disposed higher than the first wiring layer in a second direction Z across the first direction, not including the first region and including the second region; a first memory pillar MP disposed in the first region SU3 and passing the first wiring layer SGD3 in the second direction Z; and a second memory pillar MP disposed in the second region SU2 and passing the first wiring layer SGD3 and the second wiring layer SGD2 in the second direction Z.SELECTED DRAWING: Figure 4 【課題】セル集積度を向上させることができる半導体記憶装置を提供する。【解決手段】一実施形態の半導体記憶装置は、第1領域SU3及び第1領域と第1方向Yに並ぶ第2領域SU2を含む第1配線層SGD3と、第1方向と交差する第2方向Zに、第1配線層よりも上方に配置され、第1領域を含まず且つ第2領域を含む第2配線層SGD2とを有する積層配線SIと、第1領域SU3に配置され、第2方向Zに第1配線層SGD3を通過する第1メモリピラーMPと、第2領域SU2に配置され、第2方向Zに第1配線層SGD3及び第2配線層SGD2を通過する第2メモリピラーMPとを備える。【選択図】図4