SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
To provide a semiconductor device with reduced warpage.SOLUTION: A semiconductor device 100A includes an interlayer insulating film 33, and a wiring 53 of an uppermost layer arranged on the interlayer insulating film 33. The wiring 53 includes a seed layer 53a arranged on the interlayer insulating f...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; jpn |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | NII AKINORI TAKEI SHOJI |
| description | To provide a semiconductor device with reduced warpage.SOLUTION: A semiconductor device 100A includes an interlayer insulating film 33, and a wiring 53 of an uppermost layer arranged on the interlayer insulating film 33. The wiring 53 includes a seed layer 53a arranged on the interlayer insulating film 33 and a wiring body portion 53b arranged on the seed layer 53a. A constituent material of the wiring body portion 53b is copper or a copper alloy. A trench 37 is formed in an upper surface of the interlayer insulating film 33 along an outer edge of the interlayer insulating film 33 in a plan view.SELECTED DRAWING: Figure 2
【課題】反りの低減された半導体装置を提供する。【解決手段】半導体装置１００Ａは、層間絶縁膜３３と、層間絶縁膜３３上に配置されている最上層の配線５３とを備える。配線５３は、層間絶縁膜３３上に配置されているシード層５３ａと、シード層５３ａ上に配置されている配線本体部５３ｂとを有する。配線本体部５３ｂの構成材料は、銅又は銅合金である。層間絶縁膜３３の上面には、層間絶縁膜３３の平面視における外周縁に沿って溝３７が形成されている。【選択図】図２ |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2024031397A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2024031397A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2024031397A3</originalsourceid><addsrcrecordid>eNrjZHALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrYNPBw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDIxMDIwNjS3NHY2JUgQAG6ws7A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>NII AKINORI ; TAKEI SHOJI</creator><creatorcontrib>NII AKINORI ; TAKEI SHOJI</creatorcontrib><description>To provide a semiconductor device with reduced warpage.SOLUTION: A semiconductor device 100A includes an interlayer insulating film 33, and a wiring 53 of an uppermost layer arranged on the interlayer insulating film 33. The wiring 53 includes a seed layer 53a arranged on the interlayer insulating film 33 and a wiring body portion 53b arranged on the seed layer 53a. A constituent material of the wiring body portion 53b is copper or a copper alloy. A trench 37 is formed in an upper surface of the interlayer insulating film 33 along an outer edge of the interlayer insulating film 33 in a plan view.SELECTED DRAWING: Figure 2
【課題】反りの低減された半導体装置を提供する。【解決手段】半導体装置１００Ａは、層間絶縁膜３３と、層間絶縁膜３３上に配置されている最上層の配線５３とを備える。配線５３は、層間絶縁膜３３上に配置されているシード層５３ａと、シード層５３ａ上に配置されている配線本体部５３ｂとを有する。配線本体部５３ｂの構成材料は、銅又は銅合金である。層間絶縁膜３３の上面には、層間絶縁膜３３の平面視における外周縁に沿って溝３７が形成されている。【選択図】図２</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240307&DB=EPODOC&CC=JP&NR=2024031397A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240307&DB=EPODOC&CC=JP&NR=2024031397A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NII AKINORI</creatorcontrib><creatorcontrib>TAKEI SHOJI</creatorcontrib><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><description>To provide a semiconductor device with reduced warpage.SOLUTION: A semiconductor device 100A includes an interlayer insulating film 33, and a wiring 53 of an uppermost layer arranged on the interlayer insulating film 33. The wiring 53 includes a seed layer 53a arranged on the interlayer insulating film 33 and a wiring body portion 53b arranged on the seed layer 53a. A constituent material of the wiring body portion 53b is copper or a copper alloy. A trench 37 is formed in an upper surface of the interlayer insulating film 33 along an outer edge of the interlayer insulating film 33 in a plan view.SELECTED DRAWING: Figure 2
【課題】反りの低減された半導体装置を提供する。【解決手段】半導体装置１００Ａは、層間絶縁膜３３と、層間絶縁膜３３上に配置されている最上層の配線５３とを備える。配線５３は、層間絶縁膜３３上に配置されているシード層５３ａと、シード層５３ａ上に配置されている配線本体部５３ｂとを有する。配線本体部５３ｂの構成材料は、銅又は銅合金である。層間絶縁膜３３の上面には、層間絶縁膜３３の平面視における外周縁に沿って溝３７が形成されている。【選択図】図２</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrYNPBw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDIxMDIwNjS3NHY2JUgQAG6ws7A</recordid><startdate>20240307</startdate><enddate>20240307</enddate><creator>NII AKINORI</creator><creator>TAKEI SHOJI</creator><scope>EVB</scope></search><sort><creationdate>20240307</creationdate><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><author>NII AKINORI ; TAKEI SHOJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2024031397A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NII AKINORI</creatorcontrib><creatorcontrib>TAKEI SHOJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NII AKINORI</au><au>TAKEI SHOJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><date>2024-03-07</date><risdate>2024</risdate><abstract>To provide a semiconductor device with reduced warpage.SOLUTION: A semiconductor device 100A includes an interlayer insulating film 33, and a wiring 53 of an uppermost layer arranged on the interlayer insulating film 33. The wiring 53 includes a seed layer 53a arranged on the interlayer insulating film 33 and a wiring body portion 53b arranged on the seed layer 53a. A constituent material of the wiring body portion 53b is copper or a copper alloy. A trench 37 is formed in an upper surface of the interlayer insulating film 33 along an outer edge of the interlayer insulating film 33 in a plan view.SELECTED DRAWING: Figure 2
【課題】反りの低減された半導体装置を提供する。【解決手段】半導体装置１００Ａは、層間絶縁膜３３と、層間絶縁膜３３上に配置されている最上層の配線５３とを備える。配線５３は、層間絶縁膜３３上に配置されているシード層５３ａと、シード層５３ａ上に配置されている配線本体部５３ｂとを有する。配線本体部５３ｂの構成材料は、銅又は銅合金である。層間絶縁膜３３の上面には、層間絶縁膜３３の平面視における外周縁に沿って溝３７が形成されている。【選択図】図２</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; jpn |
| recordid | cdi_epo_espacenet_JP2024031397A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T01%3A04%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NII%20AKINORI&rft.date=2024-03-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2024031397A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |