DATA PROCESSING ENGINE ARRANGEMENT IN DEVICE
To provide an integrated circuit device (a device) that includes one or more Data Processing Engines (DPE) and/or a DPE array.SOLUTION: A device includes a plurality of DPEs 304. Each of the DPEs includes a core 602 and a memory module 604. The plurality of DPEs are organized in one or a plurality o...
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| creator | KORNELIS A VISSERS RALPH D WITTIG JAN LANGER JUAN JOSE NOGUERA SERRA GORAN HK BILSKI TIM TUAN RICHARD L WALKE DAVID CLARK PHILIP B JAMES-ROXBY CHRISTOPHER H DICK BARIS OZGUL |
| description | To provide an integrated circuit device (a device) that includes one or more Data Processing Engines (DPE) and/or a DPE array.SOLUTION: A device includes a plurality of DPEs 304. Each of the DPEs includes a core 602 and a memory module 604. The plurality of DPEs are organized in one or a plurality of rows and one or a plurality of columns. Each core is configured to communicate with the other neighboring DPE by shared access to the memory modules of the DPE among the plurality of DPEs.SELECTED DRAWING: Figure 6
【課題】１つまたは複数のデータ処理エンジン（ＤＰＥ）および／またはＤＰＥアレイを含む集積回路デバイス（デバイス）を提供する。【解決手段】デバイスは、ＤＰＥ３０４を複数含む。ＤＰＥのそれぞれは、コア６０２およびメモリモジュール６０４を含み、複数のＤＰＥは、１つまたは複数の行および１つまたは複数の列に編成され、各コアは、複数のＤＰＥのうちの他の近傍のＤＰＥのメモリモジュールへの共有アクセスによって、当該他の近傍のＤＰＥと通信する。【選択図】図６ |
| format | Patent |
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【課題】１つまたは複数のデータ処理エンジン（ＤＰＥ）および／またはＤＰＥアレイを含む集積回路デバイス（デバイス）を提供する。【解決手段】デバイスは、ＤＰＥ３０４を複数含む。ＤＰＥのそれぞれは、コア６０２およびメモリモジュール６０４を含み、複数のＤＰＥは、１つまたは複数の行および１つまたは複数の列に編成され、各コアは、複数のＤＰＥのうちの他の近傍のＤＰＥのメモリモジュールへの共有アクセスによって、当該他の近傍のＤＰＥと通信する。【選択図】図６</description><language>eng ; jpn</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231212&DB=EPODOC&CC=JP&NR=2023175936A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231212&DB=EPODOC&CC=JP&NR=2023175936A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KORNELIS A VISSERS</creatorcontrib><creatorcontrib>RALPH D WITTIG</creatorcontrib><creatorcontrib>JAN LANGER</creatorcontrib><creatorcontrib>JUAN JOSE NOGUERA SERRA</creatorcontrib><creatorcontrib>GORAN HK BILSKI</creatorcontrib><creatorcontrib>TIM TUAN</creatorcontrib><creatorcontrib>RICHARD L WALKE</creatorcontrib><creatorcontrib>DAVID CLARK</creatorcontrib><creatorcontrib>PHILIP B JAMES-ROXBY</creatorcontrib><creatorcontrib>CHRISTOPHER H DICK</creatorcontrib><creatorcontrib>BARIS OZGUL</creatorcontrib><title>DATA PROCESSING ENGINE ARRANGEMENT IN DEVICE</title><description>To provide an integrated circuit device (a device) that includes one or more Data Processing Engines (DPE) and/or a DPE array.SOLUTION: A device includes a plurality of DPEs 304. Each of the DPEs includes a core 602 and a memory module 604. The plurality of DPEs are organized in one or a plurality of rows and one or a plurality of columns. Each core is configured to communicate with the other neighboring DPE by shared access to the memory modules of the DPE among the plurality of DPEs.SELECTED DRAWING: Figure 6
【課題】１つまたは複数のデータ処理エンジン（ＤＰＥ）および／またはＤＰＥアレイを含む集積回路デバイス（デバイス）を提供する。【解決手段】デバイスは、ＤＰＥ３０４を複数含む。ＤＰＥのそれぞれは、コア６０２およびメモリモジュール６０４を含み、複数のＤＰＥは、１つまたは複数の行および１つまたは複数の列に編成され、各コアは、複数のＤＰＥのうちの他の近傍のＤＰＥのメモリモジュールへの共有アクセスによって、当該他の近傍のＤＰＥと通信する。【選択図】図６</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBxcQxxVAgI8nd2DQ729HNXcPVz9_RzVXAMCnL0c3f1dfULUfD0U3BxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRsaG5qaWxmaOxkQpAgDOryV7</recordid><startdate>20231212</startdate><enddate>20231212</enddate><creator>KORNELIS A VISSERS</creator><creator>RALPH D WITTIG</creator><creator>JAN LANGER</creator><creator>JUAN JOSE NOGUERA SERRA</creator><creator>GORAN HK BILSKI</creator><creator>TIM TUAN</creator><creator>RICHARD L WALKE</creator><creator>DAVID CLARK</creator><creator>PHILIP B JAMES-ROXBY</creator><creator>CHRISTOPHER H DICK</creator><creator>BARIS OZGUL</creator><scope>EVB</scope></search><sort><creationdate>20231212</creationdate><title>DATA PROCESSING ENGINE ARRANGEMENT IN DEVICE</title><author>KORNELIS A VISSERS ; RALPH D WITTIG ; JAN LANGER ; JUAN JOSE NOGUERA SERRA ; GORAN HK BILSKI ; TIM TUAN ; RICHARD L WALKE ; DAVID CLARK ; PHILIP B JAMES-ROXBY ; CHRISTOPHER H DICK ; BARIS OZGUL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2023175936A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>KORNELIS A VISSERS</creatorcontrib><creatorcontrib>RALPH D WITTIG</creatorcontrib><creatorcontrib>JAN LANGER</creatorcontrib><creatorcontrib>JUAN JOSE NOGUERA SERRA</creatorcontrib><creatorcontrib>GORAN HK BILSKI</creatorcontrib><creatorcontrib>TIM TUAN</creatorcontrib><creatorcontrib>RICHARD L WALKE</creatorcontrib><creatorcontrib>DAVID CLARK</creatorcontrib><creatorcontrib>PHILIP B JAMES-ROXBY</creatorcontrib><creatorcontrib>CHRISTOPHER H DICK</creatorcontrib><creatorcontrib>BARIS OZGUL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KORNELIS A VISSERS</au><au>RALPH D WITTIG</au><au>JAN LANGER</au><au>JUAN JOSE NOGUERA SERRA</au><au>GORAN HK BILSKI</au><au>TIM TUAN</au><au>RICHARD L WALKE</au><au>DAVID CLARK</au><au>PHILIP B JAMES-ROXBY</au><au>CHRISTOPHER H DICK</au><au>BARIS OZGUL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DATA PROCESSING ENGINE ARRANGEMENT IN DEVICE</title><date>2023-12-12</date><risdate>2023</risdate><abstract>To provide an integrated circuit device (a device) that includes one or more Data Processing Engines (DPE) and/or a DPE array.SOLUTION: A device includes a plurality of DPEs 304. Each of the DPEs includes a core 602 and a memory module 604. The plurality of DPEs are organized in one or a plurality of rows and one or a plurality of columns. Each core is configured to communicate with the other neighboring DPE by shared access to the memory modules of the DPE among the plurality of DPEs.SELECTED DRAWING: Figure 6
【課題】１つまたは複数のデータ処理エンジン（ＤＰＥ）および／またはＤＰＥアレイを含む集積回路デバイス（デバイス）を提供する。【解決手段】デバイスは、ＤＰＥ３０４を複数含む。ＤＰＥのそれぞれは、コア６０２およびメモリモジュール６０４を含み、複数のＤＰＥは、１つまたは複数の行および１つまたは複数の列に編成され、各コアは、複数のＤＰＥのうちの他の近傍のＤＰＥのメモリモジュールへの共有アクセスによって、当該他の近傍のＤＰＥと通信する。【選択図】図６</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | DATA PROCESSING ENGINE ARRANGEMENT IN DEVICE |
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