DATA PROCESSING ENGINE ARRANGEMENT IN DEVICE

To provide an integrated circuit device (a device) that includes one or more Data Processing Engines (DPE) and/or a DPE array.SOLUTION: A device includes a plurality of DPEs 304. Each of the DPEs includes a core 602 and a memory module 604. The plurality of DPEs are organized in one or a plurality o...

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Hauptverfasser: KORNELIS A VISSERS, RALPH D WITTIG, JAN LANGER, JUAN JOSE NOGUERA SERRA, GORAN HK BILSKI, TIM TUAN, RICHARD L WALKE, DAVID CLARK, PHILIP B JAMES-ROXBY, CHRISTOPHER H DICK, BARIS OZGUL
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide an integrated circuit device (a device) that includes one or more Data Processing Engines (DPE) and/or a DPE array.SOLUTION: A device includes a plurality of DPEs 304. Each of the DPEs includes a core 602 and a memory module 604. The plurality of DPEs are organized in one or a plurality of rows and one or a plurality of columns. Each core is configured to communicate with the other neighboring DPE by shared access to the memory modules of the DPE among the plurality of DPEs.SELECTED DRAWING: Figure 6 【課題】1つまたは複数のデータ処理エンジン(DPE)および/またはDPEアレイを含む集積回路デバイス(デバイス)を提供する。【解決手段】デバイスは、DPE304を複数含む。DPEのそれぞれは、コア602およびメモリモジュール604を含み、複数のDPEは、1つまたは複数の行および1つまたは複数の列に編成され、各コアは、複数のDPEのうちの他の近傍のDPEのメモリモジュールへの共有アクセスによって、当該他の近傍のDPEと通信する。【選択図】図6