SEMICONDUCTOR DEVICE

To reduce parasitic capacitance in a source region and a drain region.SOLUTION: A semiconductor device includes: a semiconductor layer 22 including a first face 22u; a well region 23 formed on the first face 22u; an element separation region 24 which is formed in a frame shape enclosing the well region 23 and in contact with the well region 23 and defines an active region 25 in a surface part of the well region 23; a main gate electrode 27 which extends in a Y direction in parallel with the first face 22u on the active region 25 and of which ends 271 and 272 in the Y direction are disposed on the element separation region 24; dummy gate electrodes 32 and 34 which are disposed between the main gate electrode 27 and ends 231 and 232 of the well region 23 in an X direction orthogonal to the Y direction in a view in a Z direction vertical to the first face 22u and extends in the Y direction; and a source region 41 and a drain region 42 which are formed in a surface part of the active region 25 and disposed between the main gate electrode 27 and the dummy gate electrodes 32 and 34 in the view in the Z direction.SELECTED DRAWING: Figure 2 【課題】ソース領域およびドレイン領域における寄生容量を低減すること。【解決手段】半導体装置は、第１面２２ｕを有する半導体層２２と、第１面２２ｕに形成されたウエル領域２３と、ウエル領域２３を囲む枠状に形成され、ウエル領域２３に接し、ウエル領域２３の表面部に活性領域２５を区画する素子分離領域２４と、活性領域２５上において第１面２２ｕと平行なＹ方向に延び、Ｙ方向における端部２７１，２７２が素子分離領域２４の上に配置されたメインゲート電極２７と、第１面２２ｕに垂直なＺ方向から視てＹ方向と直交するＸ方向においてメインゲート電極２７とウエル領域２３の端部２３１，２３２との間に配置され、Ｙ方向に延びたダミーゲート電極３２，３４と、活性領域２５の表面部に形成され、Ｚ方向から視てメインゲート電極２７とダミーゲート電極３２，３４との間に配置されたソース領域４１およびドレイン領域４２と、を含む。【選択図】図２