SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
To suppress local polishing in the manufacturing process of semiconductor devices.SOLUTION: A semiconductor device has a base substrate B including a wiring layer, and chips C1, C2, C3, C4, C5, and C6 on the base substrate B, and electrodes and protective film P are provided between the chips C1, C2...
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| creator | HONGO SATOSHI UDA TATSUO TOYODA GEN |
| description | To suppress local polishing in the manufacturing process of semiconductor devices.SOLUTION: A semiconductor device has a base substrate B including a wiring layer, and chips C1, C2, C3, C4, C5, and C6 on the base substrate B, and electrodes and protective film P are provided between the chips C1, C2, C3, C4, C5, and C6, and the protective film P is also provided on the sides.SELECTED DRAWING: Figure 1
【課題】半導体装置の製造工程における局所研磨を抑制する。【解決手段】半導体装置であって、配線層を含むベース基板Ｂと、ベース基板Ｂ上に設けられたチップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６と、を備え、チップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６間に電極及び保護膜Ｐが設けられ、側面にも保護膜Ｐが設けられている。【選択図】図１ |
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【課題】半導体装置の製造工程における局所研磨を抑制する。【解決手段】半導体装置であって、配線層を含むベース基板Ｂと、ベース基板Ｂ上に設けられたチップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６と、を備え、チップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６間に電極及び保護膜Ｐが設けられ、側面にも保護膜Ｐが設けられている。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231004&DB=EPODOC&CC=JP&NR=2023139736A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231004&DB=EPODOC&CC=JP&NR=2023139736A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HONGO SATOSHI</creatorcontrib><creatorcontrib>UDA TATSUO</creatorcontrib><creatorcontrib>TOYODA GEN</creatorcontrib><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><description>To suppress local polishing in the manufacturing process of semiconductor devices.SOLUTION: A semiconductor device has a base substrate B including a wiring layer, and chips C1, C2, C3, C4, C5, and C6 on the base substrate B, and electrodes and protective film P are provided between the chips C1, C2, C3, C4, C5, and C6, and the protective film P is also provided on the sides.SELECTED DRAWING: Figure 1
【課題】半導体装置の製造工程における局所研磨を抑制する。【解決手段】半導体装置であって、配線層を含むベース基板Ｂと、ベース基板Ｂ上に設けられたチップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６と、を備え、チップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６間に電極及び保護膜Ｐが設けられ、側面にも保護膜Ｐが設けられている。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrYNPBw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDIyMDY0tzY3NHI2JUgQAHLUs9g</recordid><startdate>20231004</startdate><enddate>20231004</enddate><creator>HONGO SATOSHI</creator><creator>UDA TATSUO</creator><creator>TOYODA GEN</creator><scope>EVB</scope></search><sort><creationdate>20231004</creationdate><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><author>HONGO SATOSHI ; UDA TATSUO ; TOYODA GEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2023139736A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HONGO SATOSHI</creatorcontrib><creatorcontrib>UDA TATSUO</creatorcontrib><creatorcontrib>TOYODA GEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HONGO SATOSHI</au><au>UDA TATSUO</au><au>TOYODA GEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><date>2023-10-04</date><risdate>2023</risdate><abstract>To suppress local polishing in the manufacturing process of semiconductor devices.SOLUTION: A semiconductor device has a base substrate B including a wiring layer, and chips C1, C2, C3, C4, C5, and C6 on the base substrate B, and electrodes and protective film P are provided between the chips C1, C2, C3, C4, C5, and C6, and the protective film P is also provided on the sides.SELECTED DRAWING: Figure 1
【課題】半導体装置の製造工程における局所研磨を抑制する。【解決手段】半導体装置であって、配線層を含むベース基板Ｂと、ベース基板Ｂ上に設けられたチップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６と、を備え、チップＣ１，Ｃ２，Ｃ３，Ｃ４，Ｃ５，Ｃ６間に電極及び保護膜Ｐが設けられ、側面にも保護膜Ｐが設けられている。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
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