SEMICONDUCTOR DEVICE

To provide a semiconductor device having a configuration that can suppress reduction in electric characteristics that becomes remarkable with microfabrication.SOLUTION: A semiconductor device comprises: an oxide semiconductor layer in which a first oxide semiconductor layer, a second oxide semicondu...

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Bibliographische Detailangaben
Hauptverfasser: SEKINE WATARU, SHINOHARA SOJI, MATSUBAYASHI DAISUKE
Format: Patent
Sprache:eng ; jpn
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Beschreibung
Zusammenfassung:To provide a semiconductor device having a configuration that can suppress reduction in electric characteristics that becomes remarkable with microfabrication.SOLUTION: A semiconductor device comprises: an oxide semiconductor layer in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are laminated on a substrate in this order from the substrate side; a source electrode layer and a drain electrode layer contacted with the oxide semiconductor layer; a gate insulating film formed on the oxide semiconductor layer, the source electrode layer and the drain electrode layer; and a gate electrode layer formed on the gate insulating film. The first oxide semiconductor layer has a first region. The gate insulating film has a second region. When a film thickness of the first region is defined as TS1, and a film thickness of the second region is defined as TGI, a relation of TS1≥TGI is satisfied.SELECTED DRAWING: Figure 1 【課題】微細化に伴い顕著となる電気特性の低下を抑制できる構成の半導体装置を提供する。【解決手段】基板上に基板側から第1の酸化物半導体層、第2の酸化物半導体層、第3の酸化物半導体層の順で積層した酸化物半導体層と、酸化物半導体層と接するソース電極層およびドレイン電極層と、酸化物半導体層、ソース電極層およびドレイン電極層上に形成されたゲート絶縁膜と、ゲート絶縁膜上に形成されたゲート電極層と、を有し、第1の酸化物半導体層は第1の領域を有し、ゲート絶縁膜は第2の領域を有し、第1の領域の膜厚をTS1、第2の領域の膜厚をTGIとするとき、TS1≧TGIとする。【選択図】図1