VARIABLE DELAY CIRCUIT, VARIABLE DELAY METHOD, SIGNAL GENERATION DEVICE AND SIGNAL GENERATION METHOD

To suppress a change of an output amplitude caused by bias voltage dependence in a high frequency.SOLUTION: A branch/synthesis section 4 consists of: a first amplifier circuit 11 of a minimum delay side route r1 consisting of a current mode logic circuit 11a; and a second amplifier circuit 12 of a maximum delay side route r2 consisting of a current mode logic circuit 12a of a first stage, an emitter follower circuit 12b and a current mode logic circuit 12c of a second stage. Frequency characteristics of the maximum delay side route r2 are compensated by connecting a capacitor C in parallel with resistors R3 and R4 between emitters of the current mode logic circuits 12a and 12c of the first stage and the second stage of the maximum delay side route r2, and a delay amount is implemented by connecting a transmission line Z between output of the emitter follower circuit 12b and input of the current mode logic circuit 12c of the second stage of the maximum delay side route r2.SELECTED DRAWING: Figure 3 【課題】高周波におけるバイアス電圧依存による出力振幅の変化を抑制する。【解決手段】分岐合成部４は、カレントモードロジック回路１１ａからなる最小遅延側経路ｒ１の第１のアンプ回路１１と、１段目のカレントモードロジック回路１２ａ、エミッタフォロワ回路１２ｂ、２段目のカレントモードロジック回路１２ｃからなる最大遅延側経路ｒ２の第２のアンプ回路１２とから構成される。最大遅延側経路ｒ２の１段目と２段目のカレントモードロジック回路１２ａ，１２ｃのエミッタ間の抵抗Ｒ３，Ｒ４と並列にコンデンサＣを接続して最大遅延側経路ｒ２の周波数特性を補償し、最大遅延側経路ｒ２のエミッタフォロワ回路１２ｂの出力と２段目のカレントモードロジック回路１２ｃの入力間に伝送線路Ｚを接続して遅延量を補う。【選択図】図３