SEMICONDUCTOR STORAGE DEVICE

To improve a withstand voltage of a contact.SOLUTION: A semiconductor storage device 1 of an embodiment comprises a laminate LM in which a plurality of first conductive layers WL and a plurality of first insulation layers OL are alternately laminated layer by layer, and a through contact C4 extending in the laminate LM in a lamination direction and connecting configurations arranged on an upper and lower side in the lamination direction. The through contact C4 comprises a second conductive layer 21 extending in the lamination direction in the laminate LM and serving as a core material of the through contact C4, and a second insulation layer 55 covering a side wall of the second conductive layer 21 and serving as a liner of the through contact C4. Variations in a circumferential direction of the through contact C4 of a first distance from a center point of the second conductive layer 21 to an outer edge part of the second insulation layer 55 in a cross section in a direction crossing the lamination direction at a position adjacent to a configuration arranged at least on the lower side in the lamination direction in the through contact C4 are greater than variations in a circumferential direction of a second distance to an outer edge part of the second conductive layer 21 from the center point.SELECTED DRAWING: Figure 2 【課題】コンタクトの耐圧を向上させること。【解決手段】実施形態の半導体記憶装置１は、複数の第１の導電層ＷＬと複数の第１の絶縁層ＯＬとが１層ずつ交互に積層された積層体ＬＭと、積層体ＬＭ内を積層方向に延び、積層方向の上下側に配置される構成同士を接続する貫通コンタクトＣ４と、を備え、貫通コンタクトＣ４は、積層体ＬＭ内を積層方向に延び、貫通コンタクトＣ４の芯材となる第２の導電層２１と、第２の導電層２１の側壁を覆い、貫通コンタクトＣ４のライナとなる第２の絶縁層５５と、を有し、貫通コンタクトＣ４における少なくとも積層方向の下側に配置される構成と近接した位置で、積層方向に交差する方向の断面における第２の導電層２１の中心点から第２の絶縁層５５の外縁部までの第１の距離の貫通コンタクトＣ４の周方向におけるばらつきは、中心点から第２の導電層２１の外縁部までの第２の距離の周方向におけるばらつきよりも大きい。【選択図】図２