SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME

To provide a semiconductor storage device with a simplified manufacturing process.SOLUTION: A semiconductor storage device of an embodiment includes a first chip 40 and a second chip 50. The first chip includes a plurality of first conductive layers having intervals and arranged in a first direction...

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1. Verfasser: KUME IPPEI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a semiconductor storage device with a simplified manufacturing process.SOLUTION: A semiconductor storage device of an embodiment includes a first chip 40 and a second chip 50. The first chip includes a plurality of first conductive layers having intervals and arranged in a first direction; a first semiconductor layer extending in the plurality of first conductive layers in the first direction; a first insulation film between the first semiconductor layer and the plurality of first conductive layers; a second semiconductor layer 41 provided above the plurality of first conductive layers and in contact with the first semiconductor layer; and a first electrode PD3a provided above and in contact with the second semiconductor layer. The second chip includes a second electrode PD4 in contact with the first electrode, and a second conductive layer 51 in contact with the second electrode.SELECTED DRAWING: Figure 3 【課題】製造工程が簡素化された半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置は、間隔を有して第1方向に並ぶ複数の第1導電層と、前記複数の第1導電層内を前記第1方向に延びる第1半導体層と、前記第1半導体層と前記複数の第1導電層との間の第1絶縁膜と、前記複数の第1導電層の上方に設けられ、前記第1半導体層に接する第2半導体層41と、前記第2半導体層の上方に接して設けられた第1電極PD3aとを含む第1チップ40を含み、前記第1電極に接する第2電極PD4と、前記第2電極に接する第2導電層51とを含む第2チップ50を含む。【選択図】図3