SEMICONDUCTOR STORAGE DEVICE

To provide a semiconductor storage device in which fluctuations in characteristics of peripheral circuit elements are suppressed.SOLUTION: A semiconductor storage device according to an embodiment includes a plurality of first conductive layers 43 arranged in the first direction at intervals, a first plug C4 penetrating through the plurality of first conductive layers, a second conductive layer IC2a connected to the lower end of the first plug under the plurality of first conductive layers, a first transistor Tr below the plurality of first conductive layers, a second transistor AE in a second region DP between the first region below the second conductive layer and the first transistor, having the gate electrically connected to the first transistor and the drain electrically connected to the first transistor, and a third transistor AE in the second region, having the source and the drain electrically connected to each other.SELECTED DRAWING: Figure 6 【課題】周辺回路素子の特性変動が抑えられた半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置は、間隔を有して第１方向に並ぶ複数の第１導電層４３と、前記複数の第１導電層を貫く第１プラグＣ４と、前記複数の第１導電層の下方で、前記第１プラグの下端に接続される第２導電層ＩＣ２ａと、前記複数の第１導電層の下方の第１トランジスタＴｒと、前記第２導電層の下方の第１領域と前記第１トランジスタとの間の第２領域ＤＰ中の第２トランジスタＡＥであって、前記第１トランジスタに電気的に接続されるゲートおよび前記第１トランジスタに電気的に接続されるドレインを有する前記第２トランジスタと、前記第２領域中の第３トランジスタＡＥであって、互いに電気的に接続されるソースおよびドレインを有する前記第３トランジスタとを含む。【選択図】図６