SEMICONDUCTOR DEVICE

To provide a semiconductor device capable of reducing the chip size.SOLUTION: A semiconductor device 1 includes an element forming region, and an edge seal 3 formed on at least a portion of an outer edge surrounding the element forming region. The edge seal 3 includes a conductive layer M21 formed o...

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Bibliographische Detailangaben
Hauptverfasser: MIZUTA YOICHI, TSURUTO TAKAHIRO, TAKAHASHI YOSHIAKI, SHIMAMURA YOSHIFUMI, OZAWA TORU, MATOBA KENICHI, KOSAKI TAKUMI, NAKAO KOJI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a semiconductor device capable of reducing the chip size.SOLUTION: A semiconductor device 1 includes an element forming region, and an edge seal 3 formed on at least a portion of an outer edge surrounding the element forming region. The edge seal 3 includes a conductive layer M21 formed on at least a portion of the outer edge surrounding the element forming region, and a conductive layer M22 formed on at least a portion of the outer edge surrounding the element forming region. The conductive layer M21 is formed such that a voltage different from that of the conductive layer M22 may be supplied so as to form capacitance between the conductive layer M21 and the conductive layer M22 when a prescribed voltage VSS is applied to the conductive layer M22.SELECTED DRAWING: Figure 4 【課題】チップサイズを縮小化できる半導体装置を提供する。【解決手段】実施形態の半導体装置1は、素子形成領域と、素子形成領域を囲む外縁部の少なくとも一部に設けられたエッジシール3と、を有する。エッジシール3は、素子形成領域を囲む外縁部の少なくとも一部に設けられた導電層M21と、素子形成領域を囲む外縁部の少なくとも一部に設けられ、導電層M22と、を有する。導電層M21は、導電層M22に所定の電位VSSが与えられたときに導電層M21と導電層M22間に容量が形成されるように、導電層M22とは異なる電位が供給可能に形成されている。【選択図】図4