SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

To improve reliability of a semiconductor device covering an uppermost layer wiring of a multilayer wiring layer with a passivation film.SOLUTION: A semiconductor device manufacturing method forms a semiconductor device including a first wiring WR1, a second wiring WR2, dummy wirings D1 and D2, and...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MORI TAKAHIRO, KOSHIMIZU AKIRA, MURAYAMA TOMOKI, SAKAI JUNJIRO, IIDA SATOSHI
Format: Patent
Sprache:eng ; jpn
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:To improve reliability of a semiconductor device covering an uppermost layer wiring of a multilayer wiring layer with a passivation film.SOLUTION: A semiconductor device manufacturing method forms a semiconductor device including a first wiring WR1, a second wiring WR2, dummy wirings D1 and D2, and a passivation film covering those wirings as an uppermost layer wiring of a multilayer wiring layer. The passivation film is patterned by etching which uses a photoresist film, and formed densely with the first wiring WR1 and a plurality of neighboring dummy wirings D1. The dummy wiring D2 is formed to surround a periphery of the second wiring WR2 sparsely formed immediately above an analog circuit unit ANC.SELECTED DRAWING: Figure 10 【課題】多層配線層の最上層配線をパッシベーション膜により覆う半導体装置の信頼性を向上させる。【解決手段】多層配線層の最上層配線として、第1配線WR1、第2配線WR2、ダミー配線D1およびD2を有し、それらの配線を覆うパッシベーション膜を有する半導体装置を形成する。パッシベーション膜は、フォトレジスト膜を用いたエッチングによりパターニングされ、第1配線WR1とその近傍の複数のダミー配線D1とは密に形成され、ダミー配線D2は、アナログ回路部ANCの直上に疎に形成された第2配線WR2の周囲を囲むように形成される。【選択図】図10