WIRING BOARD, DISPLAY, AND METHOD FOR MANUFACTURING WIRING BOARD
To reduce wiring resistance and prevent deformation of a substrate.SOLUTION: An array substrate 12 comprises: a glass substrate 12GS; a first gate wiring forming part 15A that is composed of a first metal film F1 laminated on the glass substrate 12GS and extends along a plate surface of the glass su...
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| creator | SASAKI KAZUNARI MATSUMOTO RYUJI ICHIKAWA MASASHI ITAKURA RYOJI KAZUMI OSAMU TERAUCHI TAKASHI HAYASHI KIMIHIKO MORIHIRO KAZUTOSHI |
| description | To reduce wiring resistance and prevent deformation of a substrate.SOLUTION: An array substrate 12 comprises: a glass substrate 12GS; a first gate wiring forming part 15A that is composed of a first metal film F1 laminated on the glass substrate 12GS and extends along a plate surface of the glass substrate 12GS; a first insulating film F2 that is laminated at last on the glass substrate 12GS, the first insulating film F2 having a first opening F2A arranged to be superimposed on the first gate wiring forming part 15A and extending along the first gate wiring forming part 15A; and a second gate wiring forming part 15B that is composed of a second metal film F3 laminated at least on the first metal film F1, extends along the first gate wiring forming part 15A, and forms gate wiring 15 together with the first gate wiring forming part 15A, the second gate wiring forming part 15B arranged to be at least partially superimposed on the first opening F2A and in contact with the first gate wiring forming part 15A.SELECTED DRAWING: Figure 3
【課題】配線抵抗の低減を図るとともに基板の変形を抑制する。【解決手段】アレイ基板１２は、ガラス基板１２ＧＳと、ガラス基板１２ＧＳ上に積層される第１金属膜Ｆ１からなりガラス基板１２ＧＳの板面に沿って延在する第１ゲート配線構成部１５Ａと、少なくともガラス基板１２ＧＳ上に積層される第１絶縁膜Ｆ２であって、第１ゲート配線構成部１５Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに沿って延在する第１開口Ｆ２Ａを有する第１絶縁膜Ｆ２と、少なくとも第１金属膜Ｆ１上に積層される第２金属膜Ｆ３からなり第１ゲート配線構成部１５Ａに沿って延在していて第１ゲート配線構成部１５Ａと共にゲート配線１５を構成する第２ゲート配線構成部１５Ｂであって、少なくとも一部が第１開口Ｆ２Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに接する第２ゲート配線構成部１５Ｂと、を備える。【選択図】図３ |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2022168440A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2022168440A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2022168440A3</originalsourceid><addsrcrecordid>eNrjZHAI9wzy9HNXcPJ3DHLRUXDxDA7wcYzUUXD0c1HwdQ3x8HdRcPMPUvB19At1c3QOCQUrRtbDw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDIyMDM0sTEwMHI2JUgQA1Kwqwg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIRING BOARD, DISPLAY, AND METHOD FOR MANUFACTURING WIRING BOARD</title><source>esp@cenet</source><creator>SASAKI KAZUNARI ; MATSUMOTO RYUJI ; ICHIKAWA MASASHI ; ITAKURA RYOJI ; KAZUMI OSAMU ; TERAUCHI TAKASHI ; HAYASHI KIMIHIKO ; MORIHIRO KAZUTOSHI</creator><creatorcontrib>SASAKI KAZUNARI ; MATSUMOTO RYUJI ; ICHIKAWA MASASHI ; ITAKURA RYOJI ; KAZUMI OSAMU ; TERAUCHI TAKASHI ; HAYASHI KIMIHIKO ; MORIHIRO KAZUTOSHI</creatorcontrib><description>To reduce wiring resistance and prevent deformation of a substrate.SOLUTION: An array substrate 12 comprises: a glass substrate 12GS; a first gate wiring forming part 15A that is composed of a first metal film F1 laminated on the glass substrate 12GS and extends along a plate surface of the glass substrate 12GS; a first insulating film F2 that is laminated at last on the glass substrate 12GS, the first insulating film F2 having a first opening F2A arranged to be superimposed on the first gate wiring forming part 15A and extending along the first gate wiring forming part 15A; and a second gate wiring forming part 15B that is composed of a second metal film F3 laminated at least on the first metal film F1, extends along the first gate wiring forming part 15A, and forms gate wiring 15 together with the first gate wiring forming part 15A, the second gate wiring forming part 15B arranged to be at least partially superimposed on the first opening F2A and in contact with the first gate wiring forming part 15A.SELECTED DRAWING: Figure 3
【課題】配線抵抗の低減を図るとともに基板の変形を抑制する。【解決手段】アレイ基板１２は、ガラス基板１２ＧＳと、ガラス基板１２ＧＳ上に積層される第１金属膜Ｆ１からなりガラス基板１２ＧＳの板面に沿って延在する第１ゲート配線構成部１５Ａと、少なくともガラス基板１２ＧＳ上に積層される第１絶縁膜Ｆ２であって、第１ゲート配線構成部１５Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに沿って延在する第１開口Ｆ２Ａを有する第１絶縁膜Ｆ２と、少なくとも第１金属膜Ｆ１上に積層される第２金属膜Ｆ３からなり第１ゲート配線構成部１５Ａに沿って延在していて第１ゲート配線構成部１５Ａと共にゲート配線１５を構成する第２ゲート配線構成部１５Ｂであって、少なくとも一部が第１開口Ｆ２Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに接する第２ゲート配線構成部１５Ｂと、を備える。【選択図】図３</description><language>eng ; jpn</language><subject>ADVERTISING ; BASIC ELECTRIC ELEMENTS ; CRYPTOGRAPHY ; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING ; DISPLAY ; DISPLAYING ; EDUCATION ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FREQUENCY-CHANGING ; LABELS OR NAME-PLATES ; NON-LINEAR OPTICS ; OPTICAL ANALOGUE/DIGITAL CONVERTERS ; OPTICAL LOGIC ELEMENTS ; OPTICS ; PHYSICS ; SEALS ; SEMICONDUCTOR DEVICES ; SIGNS ; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221108&DB=EPODOC&CC=JP&NR=2022168440A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221108&DB=EPODOC&CC=JP&NR=2022168440A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SASAKI KAZUNARI</creatorcontrib><creatorcontrib>MATSUMOTO RYUJI</creatorcontrib><creatorcontrib>ICHIKAWA MASASHI</creatorcontrib><creatorcontrib>ITAKURA RYOJI</creatorcontrib><creatorcontrib>KAZUMI OSAMU</creatorcontrib><creatorcontrib>TERAUCHI TAKASHI</creatorcontrib><creatorcontrib>HAYASHI KIMIHIKO</creatorcontrib><creatorcontrib>MORIHIRO KAZUTOSHI</creatorcontrib><title>WIRING BOARD, DISPLAY, AND METHOD FOR MANUFACTURING WIRING BOARD</title><description>To reduce wiring resistance and prevent deformation of a substrate.SOLUTION: An array substrate 12 comprises: a glass substrate 12GS; a first gate wiring forming part 15A that is composed of a first metal film F1 laminated on the glass substrate 12GS and extends along a plate surface of the glass substrate 12GS; a first insulating film F2 that is laminated at last on the glass substrate 12GS, the first insulating film F2 having a first opening F2A arranged to be superimposed on the first gate wiring forming part 15A and extending along the first gate wiring forming part 15A; and a second gate wiring forming part 15B that is composed of a second metal film F3 laminated at least on the first metal film F1, extends along the first gate wiring forming part 15A, and forms gate wiring 15 together with the first gate wiring forming part 15A, the second gate wiring forming part 15B arranged to be at least partially superimposed on the first opening F2A and in contact with the first gate wiring forming part 15A.SELECTED DRAWING: Figure 3
【課題】配線抵抗の低減を図るとともに基板の変形を抑制する。【解決手段】アレイ基板１２は、ガラス基板１２ＧＳと、ガラス基板１２ＧＳ上に積層される第１金属膜Ｆ１からなりガラス基板１２ＧＳの板面に沿って延在する第１ゲート配線構成部１５Ａと、少なくともガラス基板１２ＧＳ上に積層される第１絶縁膜Ｆ２であって、第１ゲート配線構成部１５Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに沿って延在する第１開口Ｆ２Ａを有する第１絶縁膜Ｆ２と、少なくとも第１金属膜Ｆ１上に積層される第２金属膜Ｆ３からなり第１ゲート配線構成部１５Ａに沿って延在していて第１ゲート配線構成部１５Ａと共にゲート配線１５を構成する第２ゲート配線構成部１５Ｂであって、少なくとも一部が第１開口Ｆ２Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに接する第２ゲート配線構成部１５Ｂと、を備える。【選択図】図３</description><subject>ADVERTISING</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CRYPTOGRAPHY</subject><subject>DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING</subject><subject>DISPLAY</subject><subject>DISPLAYING</subject><subject>EDUCATION</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>FREQUENCY-CHANGING</subject><subject>LABELS OR NAME-PLATES</subject><subject>NON-LINEAR OPTICS</subject><subject>OPTICAL ANALOGUE/DIGITAL CONVERTERS</subject><subject>OPTICAL LOGIC ELEMENTS</subject><subject>OPTICS</subject><subject>PHYSICS</subject><subject>SEALS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SIGNS</subject><subject>TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAI9wzy9HNXcPJ3DHLRUXDxDA7wcYzUUXD0c1HwdQ3x8HdRcPMPUvB19At1c3QOCQUrRtbDw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDIyMDM0sTEwMHI2JUgQA1Kwqwg</recordid><startdate>20221108</startdate><enddate>20221108</enddate><creator>SASAKI KAZUNARI</creator><creator>MATSUMOTO RYUJI</creator><creator>ICHIKAWA MASASHI</creator><creator>ITAKURA RYOJI</creator><creator>KAZUMI OSAMU</creator><creator>TERAUCHI TAKASHI</creator><creator>HAYASHI KIMIHIKO</creator><creator>MORIHIRO KAZUTOSHI</creator><scope>EVB</scope></search><sort><creationdate>20221108</creationdate><title>WIRING BOARD, DISPLAY, AND METHOD FOR MANUFACTURING WIRING BOARD</title><author>SASAKI KAZUNARI ; MATSUMOTO RYUJI ; ICHIKAWA MASASHI ; ITAKURA RYOJI ; KAZUMI OSAMU ; TERAUCHI TAKASHI ; HAYASHI KIMIHIKO ; MORIHIRO KAZUTOSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2022168440A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2022</creationdate><topic>ADVERTISING</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CRYPTOGRAPHY</topic><topic>DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING</topic><topic>DISPLAY</topic><topic>DISPLAYING</topic><topic>EDUCATION</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>FREQUENCY-CHANGING</topic><topic>LABELS OR NAME-PLATES</topic><topic>NON-LINEAR OPTICS</topic><topic>OPTICAL ANALOGUE/DIGITAL CONVERTERS</topic><topic>OPTICAL LOGIC ELEMENTS</topic><topic>OPTICS</topic><topic>PHYSICS</topic><topic>SEALS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SIGNS</topic><topic>TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF</topic><toplevel>online_resources</toplevel><creatorcontrib>SASAKI KAZUNARI</creatorcontrib><creatorcontrib>MATSUMOTO RYUJI</creatorcontrib><creatorcontrib>ICHIKAWA MASASHI</creatorcontrib><creatorcontrib>ITAKURA RYOJI</creatorcontrib><creatorcontrib>KAZUMI OSAMU</creatorcontrib><creatorcontrib>TERAUCHI TAKASHI</creatorcontrib><creatorcontrib>HAYASHI KIMIHIKO</creatorcontrib><creatorcontrib>MORIHIRO KAZUTOSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SASAKI KAZUNARI</au><au>MATSUMOTO RYUJI</au><au>ICHIKAWA MASASHI</au><au>ITAKURA RYOJI</au><au>KAZUMI OSAMU</au><au>TERAUCHI TAKASHI</au><au>HAYASHI KIMIHIKO</au><au>MORIHIRO KAZUTOSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIRING BOARD, DISPLAY, AND METHOD FOR MANUFACTURING WIRING BOARD</title><date>2022-11-08</date><risdate>2022</risdate><abstract>To reduce wiring resistance and prevent deformation of a substrate.SOLUTION: An array substrate 12 comprises: a glass substrate 12GS; a first gate wiring forming part 15A that is composed of a first metal film F1 laminated on the glass substrate 12GS and extends along a plate surface of the glass substrate 12GS; a first insulating film F2 that is laminated at last on the glass substrate 12GS, the first insulating film F2 having a first opening F2A arranged to be superimposed on the first gate wiring forming part 15A and extending along the first gate wiring forming part 15A; and a second gate wiring forming part 15B that is composed of a second metal film F3 laminated at least on the first metal film F1, extends along the first gate wiring forming part 15A, and forms gate wiring 15 together with the first gate wiring forming part 15A, the second gate wiring forming part 15B arranged to be at least partially superimposed on the first opening F2A and in contact with the first gate wiring forming part 15A.SELECTED DRAWING: Figure 3
【課題】配線抵抗の低減を図るとともに基板の変形を抑制する。【解決手段】アレイ基板１２は、ガラス基板１２ＧＳと、ガラス基板１２ＧＳ上に積層される第１金属膜Ｆ１からなりガラス基板１２ＧＳの板面に沿って延在する第１ゲート配線構成部１５Ａと、少なくともガラス基板１２ＧＳ上に積層される第１絶縁膜Ｆ２であって、第１ゲート配線構成部１５Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに沿って延在する第１開口Ｆ２Ａを有する第１絶縁膜Ｆ２と、少なくとも第１金属膜Ｆ１上に積層される第２金属膜Ｆ３からなり第１ゲート配線構成部１５Ａに沿って延在していて第１ゲート配線構成部１５Ａと共にゲート配線１５を構成する第２ゲート配線構成部１５Ｂであって、少なくとも一部が第１開口Ｆ２Ａと重畳するよう配されて第１ゲート配線構成部１５Ａに接する第２ゲート配線構成部１５Ｂと、を備える。【選択図】図３</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ADVERTISING BASIC ELECTRIC ELEMENTS CRYPTOGRAPHY DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING DISPLAY DISPLAYING EDUCATION ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FREQUENCY-CHANGING LABELS OR NAME-PLATES NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHYSICS SEALS SEMICONDUCTOR DEVICES SIGNS TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF |
| title | WIRING BOARD, DISPLAY, AND METHOD FOR MANUFACTURING WIRING BOARD |
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