SEMICONDUCTOR STORAGE DEVICE

To provide a semiconductor storage device capable of achieving higher integration.SOLUTION: A semiconductor storage device comprises: a first conductive layer extending in a first direction; a second conductive layer extending in the first direction and juxtaposed with the first conductive layer in...

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Bibliographische Detailangaben
Hauptverfasser: OCHIAI TAKAFUMI, TORAYA KENICHIRO, HOANG HA, ISHIMARU YUKI, MORI SHINJI, HONDA SHOJI, FUKUDA NATSUKI, KURUSU TAKASHI, TAKAHASHI KOTA, NARASAKI RYOTA, MATSUO KAZUNORI, KAMIYA YUTA, SAITO YUTA, YAMASHITA HIROYUKI, KANAYAMA JUNICHI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a semiconductor storage device capable of achieving higher integration.SOLUTION: A semiconductor storage device comprises: a first conductive layer extending in a first direction; a second conductive layer extending in the first direction and juxtaposed with the first conductive layer in a second direction; a first insulation layer provided between the first conductive layer and the second conductive layer; a semiconductor layer extending in the second direction and facing the first conductive layer, the second conductive layer, and the first insulation layer in a third direction; a first charge storage layer provided between the first conductive layer and the semiconductor layer; a second charge storage layer provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer. At least a part of the first charge storage layer faces the second charge storage layer without the second high dielectric constant layer in the second direction.SELECTED DRAWING: Figure 6 【課題】高集積化が可能な半導体記憶装置を提供する。【解決手段】半導体記憶装置は、第1方向に延伸する第1導電層と、第1方向に延伸し第2方向において第1導電層と並ぶ第2導電層と、第1導電層と第2導電層との間に設けられた第1絶縁層と、第2方向に延伸し、第3方向において第1導電層、第2導電層、及び第1絶縁層と対向する半導体層と、第1導電層と半導体層との間に設けられた第1電荷蓄積層と、第2導電層と半導体層との間に設けられた第2電荷蓄積層と、第1導電層と第1電荷蓄積層との間に設けられた第1高誘電率層と、第2導電層と第2電荷蓄積層との間に設けられた第2高誘電率層とを備える。第1電荷蓄積層の少なくとも一部は、第2方向において第2高誘電率層を介さずに第2電荷蓄積層と対向する。【選択図】図6