METHOD FOR PROCESSING WAFER

To provide a method for processing a wafer capable of setting to zero or reducing the percentage of devices that are damaged by edge trimming and reducing the probability of a wafer breaking and/or the probability of a contamination source or a dust source being formed on a laminated wafer.SOLUTION:...

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Hauptverfasser: MINATO KOKICHI, HIROZAWA SHUNICHIRO
Format: Patent
Sprache:eng ; jpn
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Beschreibung
Zusammenfassung:To provide a method for processing a wafer capable of setting to zero or reducing the percentage of devices that are damaged by edge trimming and reducing the probability of a wafer breaking and/or the probability of a contamination source or a dust source being formed on a laminated wafer.SOLUTION: An outer edge portion of a wafer is processed with a width that varies in accordance with the spacing between a center of the wafer and a boundary between a device area on which a plurality of devices is formed and an outer surplus area surrounding the device area. In other words, the width of the outer edge portion to be removed by edge trimming of the wafer is set in accordance with the spacing between the boundary between the center of the wafer and the device area and the outer excess area .SELECTED DRAWING: Figure 3 【課題】エッジトリミングによって損傷するデバイスの割合を0にする又は低減するとともに、ウェーハが割れる蓋然性、及び/又は、貼り合わせウェーハにおいて汚染源若しくは発塵源が形成される蓋然性を低減することが可能なウェーハの加工方法を提供する。【解決手段】複数のデバイスが形成されたデバイス領域及びデバイス領域を囲繞する外周余剰領域の境界とウェーハの中心との間隔に応じて変動する幅でウェーハの外周端部を加工する。換言すると、ウェーハのエッジトリミングによって除去される外周端部の幅を、デバイス領域及び外周余剰領域の境界とウェーハの中心との間隔に応じて設定する。【選択図】図3