SEMICONDUCTOR INTEGRATED CIRCUIT FOR RESET, AND ELECTRONIC CIRCUIT SYSTEM INCLUDING THE SAME

To provide a reset circuit and a semiconductor integrated circuit for reset capable of modifying a delay time of a reset signal.SOLUTION: A semiconductor integrated circuit for reset that comprises a voltage detection circuit (21) and outputs a reset signal when a power supply voltage (VDD1) to be monitored becomes lower than a predetermined level, is configured to comprise: an output stage (22) consisting of a CMOS circuit that generates and outputs a signal depending on detection results of the voltage detection circuit; a monitoring voltage input terminal (VS) that receives the power supply voltage (VDD1) to be monitored; a reference potential terminal (GND) applied with a voltage that serves as a reference potential of the circuit; an external voltage terminal (VB) connected with a power supply voltage terminal of the output stage and to which a power supply voltage (VDD2) that serves as an operation voltage of the output stage can be applied from the exterior; and an output terminal (OUT) for outputting the signal generated by the output stage.SELECTED DRAWING: Figure 1 【課題】リセット信号の遅延時間の変更が可能なリセット回路及びリセット用半導体集積回路を提供する。【解決手段】電圧検出回路（２１）を備え、監視対象の電源電圧（ＶＤＤ１）が所定のレベルよりも低くなった場合にリセット信号を出力するリセット用半導体集積回路において、前記電圧検出回路の検出結果に応じた信号を生成し出力するＣＭＯＳ回路からなる出力段（２２）と、監視対象の電源電圧（ＶＤＤ１）が入力される監視電圧入力端子（ＶＳ）と、回路の基準電位となる電圧が印加される基準電位端子（ＧＮＤ）と、出力段の電源電圧端子が接続され外部より前記出力段の動作電圧となる電源電圧（ＶＤＤ２）を印加可能な外部電圧端子（ＶＢ）と、出力段が生成した信号を出力するための出力端子（ＯＵＴ）と、を備えているように構成した。【選択図】図１