SEMICONDUCTOR STORAGE DEVICE

To improve the yield of a semiconductor storage device.SOLUTION: A semiconductor storage device according to an embodiment includes a substrate 20, a source line SL, a plurality of word lines WL, a pillar MP, an outer peripheral conductive layer 62, a lower conductive layer 73, and a first contact C3L. The source line SL is provided over the substrate 20 in a core region MA. The pillar MP has its bottom reaching the source line SL, and intersection parts with the word lines WL each function as a memory cell. The outer peripheral conductive layer 62 is included in a first layer including the source line SL in a first region WR and is provided to surround the core region MA. The lower conductive layer 73 is included in a second layer D2 in the first region WR. The first contact C3L is provided on the lower conductive layer 73 so as to surround the core region MA in the first region WR, has an upper end included in the first layer, and is electrically connected to the outer peripheral conductive layer 62.SELECTED DRAWING: Figure 11 【課題】半導体記憶装置の歩留まりを向上させる。【解決手段】実施形態の半導体記憶装置は、基板２０と、ソース線ＳＬと、複数のワード線ＷＬと、ピラーＭＰと、外周導電体層６２と、下層導電体層７３と、第１コンタクトＣ３Ｌとを含む。ソース線ＳＬは、コア領域ＭＡで、基板２０の上方に設けられる。ピラーＭＰは、底部がソース線ＳＬに達し、複数のワード線ＷＬとの交差部分がそれぞれメモリセルとして機能する。外周導電体層６２は、第１領域ＷＲで、ソース線ＳＬを含む第１層に含まれ、且つコア領域ＭＡを囲むように設けられる。下層導電体層７３は、第１領域ＷＲで、第２層Ｄ２に含まれる。第１コンタクトＣ３Ｌは、第１領域ＷＲで、コア領域ＭＡを囲むように下層導電体層７３の上に設けられ、上端が第１層に含まれ、外周導電体層６２と電気的に接続される。【選択図】図１１