SEMICONDUCTOR DEVICE

To increase the ratio of a capacity region per capacity cell.SOLUTION: A semiconductor device according to an embodiment includes a plurality of power source lines extending in a first direction, and a plurality of cells arranged along the first direction and a second direction intersecting with the...

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Bibliographische Detailangaben
Hauptverfasser: SAKAI YUKINORI, SAKATA AKIO
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To increase the ratio of a capacity region per capacity cell.SOLUTION: A semiconductor device according to an embodiment includes a plurality of power source lines extending in a first direction, and a plurality of cells arranged along the first direction and a second direction intersecting with the first direction, in which the cell height, which corresponds to the size in the second direction, is an integer multiple of the distance between the power source lines that are adjacent to each other in the second direction. The cells include a function cell contributing to the function as the semiconductor device and a capacitor cell including a diffusion region with a first conductivity type and a gate electrode stacked on the diffusion region and functioning as a decoupling capacitor. The capacitor cell is formed as a multi-height cell whose cell height is twice or more the distance, and includes a plurality of overlapping regions arranged in the second direction, the region corresponding to a region of the gate electrode overlapping with the diffusion region in the stacking direction. The overlapping regions exist in a continuous well with a second conductivity type that is different from the first conductivity type.SELECTED DRAWING: Figure 1 【課題】1つの容量セルあたりの容量領域の比率を高めること。【解決手段】実施形態の半導体装置は、第1の方向に延びる複数の電源線と、第1の方向および第1の方向と交差する第2の方向に沿って配列され、第2の方向における寸法であるセルハイトが、第2の方向に互いに隣接する電源線間の距離の整数倍となっている複数のセルと、を備える半導体装置であって、複数のセルは、半導体装置としての機能に寄与する機能セルと、第1の導電型の拡散領域および拡散領域の上方に積層されるゲート電極を有し、デカップリングキャパシタとして機能する容量セルと、を含み、容量セルは、距離の2倍以上のセルハイトを有するマルチハイトセルとして構成され、積層方向において拡散領域と重なるゲート電極の領域であって、第2の方向に並んだ複数の重なり領域を有し、複数の重なり領域は、第1の導電型とは異なる第2の導電型の連続的な1つのウェル内に配置されている。【選択図】図1