COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE

To provide a compound semiconductor device capable of suppressing deterioration in element characteristics and a method for manufacturing the compound semiconductor device.SOLUTION: A compound semiconductor device comprises a laminate composed of a compound semiconductor and including a channel laye...

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Hauptverfasser: MOTOYAMA RIICHI, IWAO AKITO
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a compound semiconductor device capable of suppressing deterioration in element characteristics and a method for manufacturing the compound semiconductor device.SOLUTION: A compound semiconductor device comprises a laminate composed of a compound semiconductor and including a channel layer in which a carrier of a first conductivity type travels, a gate electrode provided on an upper surface side of the laminate, a source electrode provided on the upper surface side of the laminate, and a drain electrode provided on the upper surface side of the laminate. The laminate comprises a first low resistance layer of a second conductivity type provided in a position facing the gate electrode and in contact with the gate electrode, a first electric field relaxing layer run on one side of the source electrode and the drain electrode from the first low resistance layer and for relaxing electric field concentration on the first low resistance layer, and a first amorphous layer covering a first side surface, which is a side surface of the first electric field relaxing layer and faces one of the source electrode and the drain electrode.SELECTED DRAWING: Figure 3 【課題】素子特性の劣化を抑制することができる化合物半導体装置及び化合物半導体装置の製造方法を提供する。【解決手段】化合物半導体装置は、化合物半導体で構成され、第1導電型のキャリアが走行するチャネル層を含む積層体と、積層体の上面側に設けられたゲート電極と、積層体の上面側に設けられたソース電極と、積層体の上面側に設けられたドレイン電極と、を備える。積層体は、ゲート電極と対向する位置に設けられ、ゲート電極と接する第2導電型の第1低抵抗層と、第1低抵抗層からソース電極及びドレイン電極の一方の側へ延設され、第1低抵抗層への電界集中を緩和する第1電界緩和層と、第1電界緩和層の側面であってソース電極及びドレイン電極の一方と向かい合う第1側面を覆う第1アモルファス層と、を有する。【選択図】図3