SEMICONDUCTOR DEVICE

To reduce a variation ΔVth in threshold voltage in a thin-film transistor (TFT) formed of an oxide semiconductor.SOLUTION: A semiconductor device has a TFT formed of an oxide semiconductor. The oxide semiconductor has a channel area 104, a source area 1042, a drain area 1043, and an LDD (lightly dop...

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Hauptverfasser: HANADA AKIHIRO, KAITO TAKUO, TSUBUKI MASASHI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To reduce a variation ΔVth in threshold voltage in a thin-film transistor (TFT) formed of an oxide semiconductor.SOLUTION: A semiconductor device has a TFT formed of an oxide semiconductor. The oxide semiconductor has a channel area 104, a source area 1042, a drain area 1043, and an LDD (lightly doped drain) area 1041 between the channel area and the source area and drain area. The resistivity of the LDD area 1041 is smaller than the resistivity of the channel area and larger than the resistivity of the source area or the drain area. A source electrode 108 is formed superimposed on the source area 1042, and a drain electrode 109 is formed superimposed on the drain area 1043. The thickness of the LDD area 1041 of the oxide semiconductor is larger than the thickness of the channel area 104.SELECTED DRAWING: Figure 8 【課題】酸化物半導体による薄膜トランジスタ(TFT)において、閾値電圧の変動ΔVthを抑える。【解決手段】酸化物半導体によるTFTを有する半導体装置であって、前記酸化物半導体は、チャネル領域104、ソース領域1042、ドレイン領域1043と、前記チャネル領域と前記ソース領域及び前記ドレイン領域の間にLDD(Lightly Doped Drain)領域1041を有し、前記LDD領域1041の抵抗率は、前記チャネル領域の抵抗率よりも小さく、前記ソース領域あるいは前記ドレイン領域の抵抗率よりも大きく、ソース電極108は前記ソース領域1042と重複して形成され、ドレイン電極109は前記ドレイン領域1043と重複して形成され、前記酸化物半導体の前記LDD領域1041の厚さは、前記チャネル領域104の厚さよりも大きいことを特徴とする半導体装置。【選択図】図8