THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

To provide a three-dimensional semiconductor device with improved reliability, and a method of fabricating the same.SOLUTION: A semiconductor device includes: a conductive layer 180 disposed on a substrate 101 and including a first conductivity-type impurity; an insulating base layer 110 on the cond...

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Hauptverfasser: KIM SUNGGIL, KIM SEULYE, KIM SEONG-JIN, KIM JUNG-HWAN, KIM CHANHYOUNG
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a three-dimensional semiconductor device with improved reliability, and a method of fabricating the same.SOLUTION: A semiconductor device includes: a conductive layer 180 disposed on a substrate 101 and including a first conductivity-type impurity; an insulating base layer 110 on the conductive layer; a lower insulating film 11 on them; a stack structure LS having a plurality of gate electrodes 131 to 136 and a plurality of mold insulating layers 122, alternately stacked on the lower insulating film; a vertical structure CS including a vertical channel layer 150 penetrating through the stack structure CS and a vertical insulating layer 171 disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure CS having a first extended area EA extending in a width direction in the insulating base layer; a conductive film 185 extended in the first extended area along a front surface of the vertical channel layer from a bottom in contact with the conductive layer, and including a conductive material smiler to the conductive layer; and an isolation structure IA penetrating through the stack structure, the insulating base layer, and the conductive layer, and extending in one direction parallel to an upper surface of the substrate, wherein the isolation structure IA has a second extended area ER extended in the width direction in the insulating base layer.SELECTED DRAWING: Figure 3 【課題】信頼性を向上させた3次元半導体装置及びその製造方法を提供する。【解決手段】半導体装置は、基板101上の第1導電型不純物を含む導電層180と、導電層上の絶縁性ベース層110と、その上の下部絶縁膜11と、下部絶縁膜上に交互に積層された複数のゲート電極131〜136及び複数のモールド絶縁層122を有する積層構造体LSと、それを貫通する垂直チャネル層150、垂直チャネル層及び複数のゲート電極の間の垂直絶縁層171を含み、絶縁性ベース層内で幅方向に拡張された第1拡張領域EAを有する垂直構造体CSと、第1拡張領域において、導電層と接触する底から垂直チャネル層の表面に沿って延在し、導電層と同一の導電材料を含む導電膜185と、積層構造体、絶縁性ベース層及び導電層を貫通し、基板の上面と平行な一方向に延在し、絶縁性ベース層内で幅方向に拡張された第2拡張領域ERを有する分離構造体IAと、を含む。【選択図】図3