SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

To provide a semiconductor device and a semiconductor device manufacturing method, with which it is possible to suppress occurrence of peeling of a back metal film from a semiconductor substrate accompanying chipping.SOLUTION: A semiconductor device 10 comprises a semiconductor element 1, a semicond...

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Hauptverfasser: MURAZAKI HIROYUKI, HIDAKA YOSHIKI, SUEHIRO YOSHIYUKI
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creator MURAZAKI HIROYUKI
HIDAKA YOSHIKI
SUEHIRO YOSHIYUKI
description To provide a semiconductor device and a semiconductor device manufacturing method, with which it is possible to suppress occurrence of peeling of a back metal film from a semiconductor substrate accompanying chipping.SOLUTION: A semiconductor device 10 comprises a semiconductor element 1, a semiconductor substrate 2, and a back metal film 3. The second semiconductor substrate 2 includes a first surface 21, on which the semiconductor element 1 is arranged, and a second surface 22. The second surface 22 includes a first part 221 and a second part 222. The back metal film 3 includes: a first film part 31 that covers the first part 221; and a second film part 32 that covers the second part 222 and is adjacent to the first film part 31. The second film part 32 includes a recessed part 321 and a projecting part 322 that is adjacent to the recessed part 321. The recessed part 321 is recessed with respect to the first film part 31 in a direction from the second surface 22 toward the first surface 21. The projecting part 322 reaches a height position of the first film part 31 in a direction from the first surface 31 toward the second surface 32.SELECTED DRAWING: Figure 3 【課題】半導体基板にチッピングに伴うバックメタル膜の剥がれが発生することを抑制できる半導体装置および半導体装置の製造方法を提供する。【解決手段】半導体装置10は、半導体素子1と、半導体基板2と、バックメタル膜3とを備えている。半導体基板2は、半導体素子1が配置された第1面21と、第2面22とを含んでいる。第2面22は、第1部221と、第2部222とを含んでいる。バックメタル膜3は、第1部221を覆う第1膜部31と、第2部222を覆いかつ第1膜部31と隣り合う第2膜部32とを含んでいる。第2膜部32は、凹部321と、凹部321と隣り合う凸部322とを含んでいる。凹部321は、第2面22から第1面21に向かう方向に第1膜部31よりも凹んでいる。凸部322は、第1面31から第2面32に向かう方向に第1膜部31の高さ位置に達している。【選択図】図3
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The second semiconductor substrate 2 includes a first surface 21, on which the semiconductor element 1 is arranged, and a second surface 22. The second surface 22 includes a first part 221 and a second part 222. The back metal film 3 includes: a first film part 31 that covers the first part 221; and a second film part 32 that covers the second part 222 and is adjacent to the first film part 31. The second film part 32 includes a recessed part 321 and a projecting part 322 that is adjacent to the recessed part 321. The recessed part 321 is recessed with respect to the first film part 31 in a direction from the second surface 22 toward the first surface 21. The projecting part 322 reaches a height position of the first film part 31 in a direction from the first surface 31 toward the second surface 32.SELECTED DRAWING: Figure 3 【課題】半導体基板にチッピングに伴うバックメタル膜の剥がれが発生することを抑制できる半導体装置および半導体装置の製造方法を提供する。【解決手段】半導体装置10は、半導体素子1と、半導体基板2と、バックメタル膜3とを備えている。半導体基板2は、半導体素子1が配置された第1面21と、第2面22とを含んでいる。第2面22は、第1部221と、第2部222とを含んでいる。バックメタル膜3は、第1部221を覆う第1膜部31と、第2部222を覆いかつ第1膜部31と隣り合う第2膜部32とを含んでいる。第2膜部32は、凹部321と、凹部321と隣り合う凸部322とを含んでいる。凹部321は、第2面22から第1面21に向かう方向に第1膜部31よりも凹んでいる。凸部322は、第1面31から第2面32に向かう方向に第1膜部31の高さ位置に達している。【選択図】図3</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210222&amp;DB=EPODOC&amp;CC=JP&amp;NR=2021027154A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210222&amp;DB=EPODOC&amp;CC=JP&amp;NR=2021027154A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MURAZAKI HIROYUKI</creatorcontrib><creatorcontrib>HIDAKA YOSHIKI</creatorcontrib><creatorcontrib>SUEHIRO YOSHIYUKI</creatorcontrib><title>SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><description>To provide a semiconductor device and a semiconductor device manufacturing method, with which it is possible to suppress occurrence of peeling of a back metal film from a semiconductor substrate accompanying chipping.SOLUTION: A semiconductor device 10 comprises a semiconductor element 1, a semiconductor substrate 2, and a back metal film 3. The second semiconductor substrate 2 includes a first surface 21, on which the semiconductor element 1 is arranged, and a second surface 22. The second surface 22 includes a first part 221 and a second part 222. The back metal film 3 includes: a first film part 31 that covers the first part 221; and a second film part 32 that covers the second part 222 and is adjacent to the first film part 31. The second film part 32 includes a recessed part 321 and a projecting part 322 that is adjacent to the recessed part 321. The recessed part 321 is recessed with respect to the first film part 31 in a direction from the second surface 22 toward the first surface 21. The projecting part 322 reaches a height position of the first film part 31 in a direction from the first surface 31 toward the second surface 32.SELECTED DRAWING: Figure 3 【課題】半導体基板にチッピングに伴うバックメタル膜の剥がれが発生することを抑制できる半導体装置および半導体装置の製造方法を提供する。【解決手段】半導体装置10は、半導体素子1と、半導体基板2と、バックメタル膜3とを備えている。半導体基板2は、半導体素子1が配置された第1面21と、第2面22とを含んでいる。第2面22は、第1部221と、第2部222とを含んでいる。バックメタル膜3は、第1部221を覆う第1膜部31と、第2部222を覆いかつ第1膜部31と隣り合う第2膜部32とを含んでいる。第2膜部32は、凹部321と、凹部321と隣り合う凸部322とを含んでいる。凹部321は、第2面22から第1面21に向かう方向に第1膜部31よりも凹んでいる。凸部322は、第1面31から第2面32に向かう方向に第1膜部31の高さ位置に達している。【選択図】図3</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAKdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNRwCrh6-gX6uboHBIa5OnnruDrGuLh78LDwJqWmFOcyguluRmU3FxDnD10Uwvy41OLCxKTU_NSS-K9AowMjAwNjMwNTU0cjYlSBAByyyvT</recordid><startdate>20210222</startdate><enddate>20210222</enddate><creator>MURAZAKI HIROYUKI</creator><creator>HIDAKA YOSHIKI</creator><creator>SUEHIRO YOSHIYUKI</creator><scope>EVB</scope></search><sort><creationdate>20210222</creationdate><title>SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><author>MURAZAKI HIROYUKI ; HIDAKA YOSHIKI ; SUEHIRO YOSHIYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2021027154A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MURAZAKI HIROYUKI</creatorcontrib><creatorcontrib>HIDAKA YOSHIKI</creatorcontrib><creatorcontrib>SUEHIRO YOSHIYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MURAZAKI HIROYUKI</au><au>HIDAKA YOSHIKI</au><au>SUEHIRO YOSHIYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD</title><date>2021-02-22</date><risdate>2021</risdate><abstract>To provide a semiconductor device and a semiconductor device manufacturing method, with which it is possible to suppress occurrence of peeling of a back metal film from a semiconductor substrate accompanying chipping.SOLUTION: A semiconductor device 10 comprises a semiconductor element 1, a semiconductor substrate 2, and a back metal film 3. The second semiconductor substrate 2 includes a first surface 21, on which the semiconductor element 1 is arranged, and a second surface 22. The second surface 22 includes a first part 221 and a second part 222. The back metal film 3 includes: a first film part 31 that covers the first part 221; and a second film part 32 that covers the second part 222 and is adjacent to the first film part 31. The second film part 32 includes a recessed part 321 and a projecting part 322 that is adjacent to the recessed part 321. The recessed part 321 is recessed with respect to the first film part 31 in a direction from the second surface 22 toward the first surface 21. The projecting part 322 reaches a height position of the first film part 31 in a direction from the first surface 31 toward the second surface 32.SELECTED DRAWING: Figure 3 【課題】半導体基板にチッピングに伴うバックメタル膜の剥がれが発生することを抑制できる半導体装置および半導体装置の製造方法を提供する。【解決手段】半導体装置10は、半導体素子1と、半導体基板2と、バックメタル膜3とを備えている。半導体基板2は、半導体素子1が配置された第1面21と、第2面22とを含んでいる。第2面22は、第1部221と、第2部222とを含んでいる。バックメタル膜3は、第1部221を覆う第1膜部31と、第2部222を覆いかつ第1膜部31と隣り合う第2膜部32とを含んでいる。第2膜部32は、凹部321と、凹部321と隣り合う凸部322とを含んでいる。凹部321は、第2面22から第1面21に向かう方向に第1膜部31よりも凹んでいる。凸部322は、第1面31から第2面32に向かう方向に第1膜部31の高さ位置に達している。【選択図】図3</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
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