PLL DEVICE

To provide a PLL device capable of outputting a frequency signal having low phase noise.SOLUTION: A voltage control oscillation unit 1 oscillates an analog output signal having a frequency corresponding to a control voltage, and an ADC 21 converts the output signal into a digital signal as a feedback signal. An orthogonal demodulation unit 3 orthogonally demodulates the feedback signal to acquire an in-phase component (I component) and an orthogonal component (Q component), and a phase difference detection unit 4 obtains a phase difference between a digital frequency signal and a comparison signal on the basis of an I component and a Q component of the feedback signal and an I component and a Q component of the comparison signal having a set frequency of the output signal output from a comparison signal output unit 41. A loop filter 5 outputs a control voltage value corresponding to the phase difference, converts the control voltage value into a control voltage by a DAC 22, and supplies the control voltage to the voltage control oscillation unit 1.SELECTED DRAWING: Figure 1 【課題】位相雑音の低い周波数信号を出力することが可能なＰＬＬ装置を提供する。【解決手段】電圧制御発振部１は、制御電圧に応じた周波数を持つアナログの出力信号を発振し、ＡＤＣ２１は出力信号を帰還信号としてディジタルに変換する。直交復調部３は帰還信号を直交復調して同相成分（Ｉ成分）、直交成分（Ｑ成分）を取得し、位相差検出部４は帰還信号のＩ成分、Ｑ成分と、比較信号出力部４１から出力された出力信号の設定周波数を持つ比較信号のＩ成分、Ｑ成分とに基づき、前記ディジタル周波数信号と前記比較信号との位相差を求める。ループフィルタ５は位相差に対応する制御電圧値を出力し、ＤＡＣ２２にて制御電圧に変換して電圧制御発振部１に供給する。【選択図】図１