POWER CONVERSION DEVICE

To suppress a drive loss of a semiconductor switching element of an arm in a low load state by a driving system in a simple configuration while suppressing occurrence of a conduction loss in the semiconductor switching element.SOLUTION: In upper and lower arms of a half bridge circuit 5, gate drive power sources V1 and V2 are connected to gates of main and sub MOSFET M1 and M3 (M2 and M4) which are connected in parallel, and power MOSFET M5 and M6 are interposed between the gates of the sub power MOSFET M3 and M4 and the gate drive power sources V1 and V2. When a drive loss Pg of the power MOSFET M1-M4 becomes equal to or greater than a conduction loss Pon and output of a current sensor SI corresponding to a primary-side current IL1 flowing in a primary-side circuit 3 of a transformer T exceeds a reference voltage Ref1, the power MOSFET M5 and M6 are turned off by output of a comparator U1 which compares both of them, and the sub power MOSFET M3 and M4 are also turned off.SELECTED DRAWING: Figure 1 【課題】アームの半導体スイッチング素子における導通損失の発生を抑えつつ、低負荷状態における半導体スイッチング素子の駆動損失を簡便な構成の駆動系で抑制する。【解決手段】ハーフブリッジ回路５の上下のアームにおいて、並列接続したメイン及びサブのパワーＭＯＳＦＥＴＭ１，Ｍ３（Ｍ２，Ｍ４）のゲートにゲート駆動電源Ｖ１，Ｖ２をそれぞれ接続し、サブのパワーＭＯＳＦＥＴＭ３，Ｍ４のゲートとゲート駆動電源Ｖ１，Ｖ２との間にパワーＭＯＳＦＥＴＭ５，Ｍ６を介設する。各パワーＭＯＳＦＥＴＭ１〜Ｍ４の駆動損失Ｐｇが導通損失Ｐｏｎ以上になり、トランスＴの一次側回路３を流れる一次側電流ＩＬ１に応じた電流センサＳＩの出力が基準電圧Ｒｅｆ１を上回ると、両者を比較するコンパレータＵ１の出力によって各パワーＭＯＳＦＥＴＭ５，Ｍ６がターンオフされて、サブのパワーＭＯＳＦＥＴＭ３，Ｍ４もターンオフされる。【選択図】図１