SEMICONDUCTOR STORAGE DEVICE
To provide a semiconductor storage device capable of achieving higher integration and higher speed.SOLUTION: A semiconductor storage device according to one embodiment comprises: a substrate; a plurality of gate electrodes arranged in a first direction crossing a surface of the substrate; a first se...
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creator | KOMIYA KEN ISHIDA TAKASHI SUGANO YUJI |
description | To provide a semiconductor storage device capable of achieving higher integration and higher speed.SOLUTION: A semiconductor storage device according to one embodiment comprises: a substrate; a plurality of gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of gate electrodes; a gate insulation film provided between the gate electrode and the first semiconductor layer; a second semiconductor layer provided on a substrate side of the plurality of gate electrodes and connected to a side surface in a second direction crossing the first direction of the first semiconductor layer; and a first contact extending in the first direction and connected to the second semiconductor layer. The second semiconductor layer comprises: a first region connected to the side surface in the second direction of the first semiconductor layer and containing a P-type impurity; and a first contact region connected to the first contact and having larger N-type impurity concentration than that in the first region.SELECTED DRAWING: Figure 6
【課題】高集積化及び高速化の可能な半導体記憶装置を提供する。【解決手段】一の実施形態に係る半導体記憶装置は、基板と、基板の表面と交差する第1方向に並ぶ複数のゲート電極と、第1方向に延伸して複数のゲート電極と対向する第1半導体層と、ゲート電極及び第1半導体層の間に設けられたゲート絶縁膜と、複数のゲート電極よりも基板側に設けられ、第1半導体層の第1方向と交差する第2方向の側面に接続された第2半導体層と、第1方向に延伸し、第2半導体層に接続された第1コンタクトと、を備える。第2半導体層は、第1半導体層の第2方向の側面に接続され、P型の不純物を含む第1領域と、第1コンタクトに接続され、第1領域よりもN型の不純物の濃度が大きい第1コンタクト領域と、を備える。【選択図】図6 |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2020141076A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2020141076A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2020141076A3</originalsourceid><addsrcrecordid>eNrjZJAJdvX1dPb3cwl1DvEPUggGEo7urgourmGezq48DKxpiTnFqbxQmptByc01xNlDN7UgPz61uCAxOTUvtSTeK8DIwMjA0MTQwNzM0ZgoRQC_AyFJ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR STORAGE DEVICE</title><source>esp@cenet</source><creator>KOMIYA KEN ; ISHIDA TAKASHI ; SUGANO YUJI</creator><creatorcontrib>KOMIYA KEN ; ISHIDA TAKASHI ; SUGANO YUJI</creatorcontrib><description>To provide a semiconductor storage device capable of achieving higher integration and higher speed.SOLUTION: A semiconductor storage device according to one embodiment comprises: a substrate; a plurality of gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of gate electrodes; a gate insulation film provided between the gate electrode and the first semiconductor layer; a second semiconductor layer provided on a substrate side of the plurality of gate electrodes and connected to a side surface in a second direction crossing the first direction of the first semiconductor layer; and a first contact extending in the first direction and connected to the second semiconductor layer. The second semiconductor layer comprises: a first region connected to the side surface in the second direction of the first semiconductor layer and containing a P-type impurity; and a first contact region connected to the first contact and having larger N-type impurity concentration than that in the first region.SELECTED DRAWING: Figure 6
【課題】高集積化及び高速化の可能な半導体記憶装置を提供する。【解決手段】一の実施形態に係る半導体記憶装置は、基板と、基板の表面と交差する第1方向に並ぶ複数のゲート電極と、第1方向に延伸して複数のゲート電極と対向する第1半導体層と、ゲート電極及び第1半導体層の間に設けられたゲート絶縁膜と、複数のゲート電極よりも基板側に設けられ、第1半導体層の第1方向と交差する第2方向の側面に接続された第2半導体層と、第1方向に延伸し、第2半導体層に接続された第1コンタクトと、を備える。第2半導体層は、第1半導体層の第2方向の側面に接続され、P型の不純物を含む第1領域と、第1コンタクトに接続され、第1領域よりもN型の不純物の濃度が大きい第1コンタクト領域と、を備える。【選択図】図6</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200903&DB=EPODOC&CC=JP&NR=2020141076A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200903&DB=EPODOC&CC=JP&NR=2020141076A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOMIYA KEN</creatorcontrib><creatorcontrib>ISHIDA TAKASHI</creatorcontrib><creatorcontrib>SUGANO YUJI</creatorcontrib><title>SEMICONDUCTOR STORAGE DEVICE</title><description>To provide a semiconductor storage device capable of achieving higher integration and higher speed.SOLUTION: A semiconductor storage device according to one embodiment comprises: a substrate; a plurality of gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of gate electrodes; a gate insulation film provided between the gate electrode and the first semiconductor layer; a second semiconductor layer provided on a substrate side of the plurality of gate electrodes and connected to a side surface in a second direction crossing the first direction of the first semiconductor layer; and a first contact extending in the first direction and connected to the second semiconductor layer. The second semiconductor layer comprises: a first region connected to the side surface in the second direction of the first semiconductor layer and containing a P-type impurity; and a first contact region connected to the first contact and having larger N-type impurity concentration than that in the first region.SELECTED DRAWING: Figure 6
【課題】高集積化及び高速化の可能な半導体記憶装置を提供する。【解決手段】一の実施形態に係る半導体記憶装置は、基板と、基板の表面と交差する第1方向に並ぶ複数のゲート電極と、第1方向に延伸して複数のゲート電極と対向する第1半導体層と、ゲート電極及び第1半導体層の間に設けられたゲート絶縁膜と、複数のゲート電極よりも基板側に設けられ、第1半導体層の第1方向と交差する第2方向の側面に接続された第2半導体層と、第1方向に延伸し、第2半導体層に接続された第1コンタクトと、を備える。第2半導体層は、第1半導体層の第2方向の側面に接続され、P型の不純物を含む第1領域と、第1コンタクトに接続され、第1領域よりもN型の不純物の濃度が大きい第1コンタクト領域と、を備える。【選択図】図6</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAJdvX1dPb3cwl1DvEPUggGEo7urgourmGezq48DKxpiTnFqbxQmptByc01xNlDN7UgPz61uCAxOTUvtSTeK8DIwMjA0MTQwNzM0ZgoRQC_AyFJ</recordid><startdate>20200903</startdate><enddate>20200903</enddate><creator>KOMIYA KEN</creator><creator>ISHIDA TAKASHI</creator><creator>SUGANO YUJI</creator><scope>EVB</scope></search><sort><creationdate>20200903</creationdate><title>SEMICONDUCTOR STORAGE DEVICE</title><author>KOMIYA KEN ; ISHIDA TAKASHI ; SUGANO YUJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2020141076A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOMIYA KEN</creatorcontrib><creatorcontrib>ISHIDA TAKASHI</creatorcontrib><creatorcontrib>SUGANO YUJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOMIYA KEN</au><au>ISHIDA TAKASHI</au><au>SUGANO YUJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR STORAGE DEVICE</title><date>2020-09-03</date><risdate>2020</risdate><abstract>To provide a semiconductor storage device capable of achieving higher integration and higher speed.SOLUTION: A semiconductor storage device according to one embodiment comprises: a substrate; a plurality of gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of gate electrodes; a gate insulation film provided between the gate electrode and the first semiconductor layer; a second semiconductor layer provided on a substrate side of the plurality of gate electrodes and connected to a side surface in a second direction crossing the first direction of the first semiconductor layer; and a first contact extending in the first direction and connected to the second semiconductor layer. The second semiconductor layer comprises: a first region connected to the side surface in the second direction of the first semiconductor layer and containing a P-type impurity; and a first contact region connected to the first contact and having larger N-type impurity concentration than that in the first region.SELECTED DRAWING: Figure 6
【課題】高集積化及び高速化の可能な半導体記憶装置を提供する。【解決手段】一の実施形態に係る半導体記憶装置は、基板と、基板の表面と交差する第1方向に並ぶ複数のゲート電極と、第1方向に延伸して複数のゲート電極と対向する第1半導体層と、ゲート電極及び第1半導体層の間に設けられたゲート絶縁膜と、複数のゲート電極よりも基板側に設けられ、第1半導体層の第1方向と交差する第2方向の側面に接続された第2半導体層と、第1方向に延伸し、第2半導体層に接続された第1コンタクトと、を備える。第2半導体層は、第1半導体層の第2方向の側面に接続され、P型の不純物を含む第1領域と、第1コンタクトに接続され、第1領域よりもN型の不純物の濃度が大きい第1コンタクト領域と、を備える。【選択図】図6</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR STORAGE DEVICE |
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