SEMICONDUCTOR STORAGE DEVICE

To provide a semiconductor storage device capable of achieving higher integration and higher speed.SOLUTION: A semiconductor storage device according to one embodiment comprises: a substrate; a plurality of gate electrodes arranged in a first direction crossing a surface of the substrate; a first se...

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Bibliographische Detailangaben
Hauptverfasser: KOMIYA KEN, ISHIDA TAKASHI, SUGANO YUJI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:To provide a semiconductor storage device capable of achieving higher integration and higher speed.SOLUTION: A semiconductor storage device according to one embodiment comprises: a substrate; a plurality of gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of gate electrodes; a gate insulation film provided between the gate electrode and the first semiconductor layer; a second semiconductor layer provided on a substrate side of the plurality of gate electrodes and connected to a side surface in a second direction crossing the first direction of the first semiconductor layer; and a first contact extending in the first direction and connected to the second semiconductor layer. The second semiconductor layer comprises: a first region connected to the side surface in the second direction of the first semiconductor layer and containing a P-type impurity; and a first contact region connected to the first contact and having larger N-type impurity concentration than that in the first region.SELECTED DRAWING: Figure 6 【課題】高集積化及び高速化の可能な半導体記憶装置を提供する。【解決手段】一の実施形態に係る半導体記憶装置は、基板と、基板の表面と交差する第1方向に並ぶ複数のゲート電極と、第1方向に延伸して複数のゲート電極と対向する第1半導体層と、ゲート電極及び第1半導体層の間に設けられたゲート絶縁膜と、複数のゲート電極よりも基板側に設けられ、第1半導体層の第1方向と交差する第2方向の側面に接続された第2半導体層と、第1方向に延伸し、第2半導体層に接続された第1コンタクトと、を備える。第2半導体層は、第1半導体層の第2方向の側面に接続され、P型の不純物を含む第1領域と、第1コンタクトに接続され、第1領域よりもN型の不純物の濃度が大きい第1コンタクト領域と、を備える。【選択図】図6