FLASH TRANSLATION LAYER WITH HIERARCHICAL SECURITY

To provide apparatuses and methods for secure and reliable flash accesses of software programs that a CPU executes.SOLUTION: A computing device 100 comprises a non-volatile memory (NVM) interface 105 and a processor 103. The NVM interface 105 is configured to communicate with a flash 106. The proces...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	OMER BOTVINIK, YEHUDA BEN-SIMON, AVISHAY SHARAGA, DAVID FISHELOVICH
Format:	Patent
Sprache:	eng ; jpn
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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