SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF

To achieve both security requirements and functional safety requirements while suppressing an increase in circuit scale in a semiconductor device.SOLUTION: A semiconductor device comprises: a control unit made redundant by a plurality of processors; a memory for storing target data; a secure memory...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HOSOTANI RYO, ITO KENICHI, YAMATE AKIHIRO
Format: Patent
Sprache:eng ; jpn
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:To achieve both security requirements and functional safety requirements while suppressing an increase in circuit scale in a semiconductor device.SOLUTION: A semiconductor device comprises: a control unit made redundant by a plurality of processors; a memory for storing target data; a secure memory for storing a key used for encryption processing for encryption or decryption; an encryption unit; a secure processor for instructing the encryption unit to perform encryption processing in response to a request from the control unit; a first bus for communicatively connecting the control unit, the memory, the encryption unit and the secure processor; and a second bus for communicatively connecting the secure memory, the encryption unit and the secure processor. The control unit communicates with the memory via a predetermined error detection mechanism, and the encryption unit includes a plurality of encryption processing units for independently performing encryption processing on the target data using a key based on the instruction, respectively, and each of the plurality of encryption processing units is provided with a data transfer unit for performing data transfer with the memory via the error detection mechanism.SELECTED DRAWING: Figure 3 【課題】半導体装置における回路規模の増大を抑制しつつ、セキュリティ要件と機能安全要件とを両立させること。【解決手段】半導体装置は、複数のプロセッサにより冗長化された制御部と、対象データを記憶するメモリと、暗号化又は復号化のための暗号処理に用いる鍵を記憶するセキュアメモリと、暗号部と、制御部からの要求に応じて暗号部に対して暗号処理の指示を行うセキュアプロセッサと、制御部、メモリ、暗号部及びセキュアプロセッサを通信可能に接続する第1のバスと、セキュアメモリ、暗号部及びセキュアプロセッサを通信可能に接続する第2のバスと、を備える。制御部は、所定の誤り検出機構を介してメモリとの通信を行い、暗号部は、指示に基づいて、鍵を用いて対象データに対する暗号処理をそれぞれ独立して行う複数の暗号処理部を含み、複数の暗号処理部のそれぞれは、メモリとのデータ転送を、誤り検出機構を介して行うデータ転送部を備える。【選択図】図3