HETEROJUNCTION BIPOLAR TRANSISTOR AND SEMICONDUCTOR DEVICE

To provide an HBT (Heterojunction Bipolar Transistor) of which the destruction due to avalanche multiplication can be suppressed without involving increase in a chip size.SOLUTION: A first sub-collector layer serves as an inflow path of a collector current flowing through a collector layer of a hete...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: OBE ISAO, TSUTSUI TAKAYUKI, TANAKA SATOSHI, UMEMOTO YASUNARI
Format: Patent
Sprache:eng ; jpn
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!