SEMICONDUCTOR DEVICE
To provide a semiconductor device capable of suppressing occurrence of electrical connection failure when mounted on an external substrate.SOLUTION: A semiconductor device includes: a semiconductor substrate; a plurality of first bipolar transistors provided on a first main surface side of the semic...
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| creator | KOYA SHIGEKI OBE ISAO TSUTSUI TAKAYUKI UMEMOTO YASUNARI |
| description | To provide a semiconductor device capable of suppressing occurrence of electrical connection failure when mounted on an external substrate.SOLUTION: A semiconductor device includes: a semiconductor substrate; a plurality of first bipolar transistors provided on a first main surface side of the semiconductor substrate and having a first height between an emitter layer and an emitter electrode in a direction perpendicular to the first main surface; at least one or more second bipolar transistors provided on the first main surface side of the semiconductor substrate and having a second height higher than the first height between the emitter layer and the emitter electrode in a direction perpendicular to the first main surface; and a first bump disposed over the plurality of first bipolar transistors and at least one or more second bipolar transistors.SELECTED DRAWING: Figure 2
【課題】外部基板に実装する際に、電気的な接続不良の発生を抑制することができる半導体装置を提供する。【解決手段】半導体装置は、半導体基板と、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で第１高さを有する複数の第１バイポーラトランジスタと、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で、第１高さよりも高い第２高さを有する少なくとも１つ以上の第２バイポーラトランジスタと、複数の第１バイポーラトランジスタと、少なくとも１つ以上の第２バイポーラトランジスタとに跨がって配置された第１バンプとを有する。【選択図】図２ |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2020013926A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2020013926A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2020013926A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRgYGhsaWRmaOxkQpAgC78x8Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>KOYA SHIGEKI ; OBE ISAO ; TSUTSUI TAKAYUKI ; UMEMOTO YASUNARI</creator><creatorcontrib>KOYA SHIGEKI ; OBE ISAO ; TSUTSUI TAKAYUKI ; UMEMOTO YASUNARI</creatorcontrib><description>To provide a semiconductor device capable of suppressing occurrence of electrical connection failure when mounted on an external substrate.SOLUTION: A semiconductor device includes: a semiconductor substrate; a plurality of first bipolar transistors provided on a first main surface side of the semiconductor substrate and having a first height between an emitter layer and an emitter electrode in a direction perpendicular to the first main surface; at least one or more second bipolar transistors provided on the first main surface side of the semiconductor substrate and having a second height higher than the first height between the emitter layer and the emitter electrode in a direction perpendicular to the first main surface; and a first bump disposed over the plurality of first bipolar transistors and at least one or more second bipolar transistors.SELECTED DRAWING: Figure 2
【課題】外部基板に実装する際に、電気的な接続不良の発生を抑制することができる半導体装置を提供する。【解決手段】半導体装置は、半導体基板と、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で第１高さを有する複数の第１バイポーラトランジスタと、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で、第１高さよりも高い第２高さを有する少なくとも１つ以上の第２バイポーラトランジスタと、複数の第１バイポーラトランジスタと、少なくとも１つ以上の第２バイポーラトランジスタとに跨がって配置された第１バンプとを有する。【選択図】図２</description><language>eng ; jpn</language><subject>AMPLIFIERS ; BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200123&DB=EPODOC&CC=JP&NR=2020013926A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200123&DB=EPODOC&CC=JP&NR=2020013926A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOYA SHIGEKI</creatorcontrib><creatorcontrib>OBE ISAO</creatorcontrib><creatorcontrib>TSUTSUI TAKAYUKI</creatorcontrib><creatorcontrib>UMEMOTO YASUNARI</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>To provide a semiconductor device capable of suppressing occurrence of electrical connection failure when mounted on an external substrate.SOLUTION: A semiconductor device includes: a semiconductor substrate; a plurality of first bipolar transistors provided on a first main surface side of the semiconductor substrate and having a first height between an emitter layer and an emitter electrode in a direction perpendicular to the first main surface; at least one or more second bipolar transistors provided on the first main surface side of the semiconductor substrate and having a second height higher than the first height between the emitter layer and the emitter electrode in a direction perpendicular to the first main surface; and a first bump disposed over the plurality of first bipolar transistors and at least one or more second bipolar transistors.SELECTED DRAWING: Figure 2
【課題】外部基板に実装する際に、電気的な接続不良の発生を抑制することができる半導体装置を提供する。【解決手段】半導体装置は、半導体基板と、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で第１高さを有する複数の第１バイポーラトランジスタと、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で、第１高さよりも高い第２高さを有する少なくとも１つ以上の第２バイポーラトランジスタと、複数の第１バイポーラトランジスタと、少なくとも１つ以上の第２バイポーラトランジスタとに跨がって配置された第１バンプとを有する。【選択図】図２</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRgYGhsaWRmaOxkQpAgC78x8Q</recordid><startdate>20200123</startdate><enddate>20200123</enddate><creator>KOYA SHIGEKI</creator><creator>OBE ISAO</creator><creator>TSUTSUI TAKAYUKI</creator><creator>UMEMOTO YASUNARI</creator><scope>EVB</scope></search><sort><creationdate>20200123</creationdate><title>SEMICONDUCTOR DEVICE</title><author>KOYA SHIGEKI ; OBE ISAO ; TSUTSUI TAKAYUKI ; UMEMOTO YASUNARI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2020013926A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2020</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOYA SHIGEKI</creatorcontrib><creatorcontrib>OBE ISAO</creatorcontrib><creatorcontrib>TSUTSUI TAKAYUKI</creatorcontrib><creatorcontrib>UMEMOTO YASUNARI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOYA SHIGEKI</au><au>OBE ISAO</au><au>TSUTSUI TAKAYUKI</au><au>UMEMOTO YASUNARI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2020-01-23</date><risdate>2020</risdate><abstract>To provide a semiconductor device capable of suppressing occurrence of electrical connection failure when mounted on an external substrate.SOLUTION: A semiconductor device includes: a semiconductor substrate; a plurality of first bipolar transistors provided on a first main surface side of the semiconductor substrate and having a first height between an emitter layer and an emitter electrode in a direction perpendicular to the first main surface; at least one or more second bipolar transistors provided on the first main surface side of the semiconductor substrate and having a second height higher than the first height between the emitter layer and the emitter electrode in a direction perpendicular to the first main surface; and a first bump disposed over the plurality of first bipolar transistors and at least one or more second bipolar transistors.SELECTED DRAWING: Figure 2
【課題】外部基板に実装する際に、電気的な接続不良の発生を抑制することができる半導体装置を提供する。【解決手段】半導体装置は、半導体基板と、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で第１高さを有する複数の第１バイポーラトランジスタと、半導体基板の第１主面側に設けられ、第１主面に垂直な方向において、エミッタ層とエミッタ電極との間で、第１高さよりも高い第２高さを有する少なくとも１つ以上の第２バイポーラトランジスタと、複数の第１バイポーラトランジスタと、少なくとも１つ以上の第２バイポーラトランジスタとに跨がって配置された第１バンプとを有する。【選択図】図２</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | AMPLIFIERS BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR DEVICE |
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