SEMICONDUCTOR INTEGRATED CIRCUIT
To provide a semiconductor integrated circuit equipped with a flip-flop circuit capable of higher speed.SOLUTION: A semiconductor integrated circuit includes a master latch unit (54, 14) that holds or passes a data signal input on the basis of a first clock signal (C_dly, CN_dly), a slave latch unit...
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| creator | GOTO KAZUAKI |
| description | To provide a semiconductor integrated circuit equipped with a flip-flop circuit capable of higher speed.SOLUTION: A semiconductor integrated circuit includes a master latch unit (54, 14) that holds or passes a data signal input on the basis of a first clock signal (C_dly, CN_dly), a slave latch unit (16, 60) that holds or passes the data signal received from the master latch unit (54, 14) in a complementary manner with the master latch unit (54, 14)) on the basis of the second clock signal (C, CN), and a transmission period variable unit (26, 12) that varies the period through which the data signal passes in the master latch unit (54, 14).SELECTED DRAWING: Figure 1
【課題】より高速化が可能なフリップフロップ回路を備えた半導体集積回路を提供すること。【解決手段】第１のクロック信号（Ｃ＿ｄｌｙ、ＣＮ＿ｄｌｙ）に基づいて入力されたデータ信号を保持またはスルーするマスタラッチ部（５４、１４）と、第２のクロック信号（Ｃ、ＣＮ）に基づいて、マスタラッチ部（５４、１４）から受け取ったデータ信号をマスタラッチ部（５４、１４）とは相補的に保持またはスルーするスレーブラッチ部（１６、６０）と、マスタラッチ部（５４、１４）においてデータ信号のスルーする期間を可変とする透過期間可変部（２６、１２）と、を含む。【選択図】図１ |
| format | Patent |
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【課題】より高速化が可能なフリップフロップ回路を備えた半導体集積回路を提供すること。【解決手段】第１のクロック信号（Ｃ＿ｄｌｙ、ＣＮ＿ｄｌｙ）に基づいて入力されたデータ信号を保持またはスルーするマスタラッチ部（５４、１４）と、第２のクロック信号（Ｃ、ＣＮ）に基づいて、マスタラッチ部（５４、１４）から受け取ったデータ信号をマスタラッチ部（５４、１４）とは相補的に保持またはスルーするスレーブラッチ部（１６、６０）と、マスタラッチ部（５４、１４）においてデータ信号のスルーする期間を可変とする透過期間可変部（２６、１２）と、を含む。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191024&DB=EPODOC&CC=JP&NR=2019186854A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191024&DB=EPODOC&CC=JP&NR=2019186854A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GOTO KAZUAKI</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>To provide a semiconductor integrated circuit equipped with a flip-flop circuit capable of higher speed.SOLUTION: A semiconductor integrated circuit includes a master latch unit (54, 14) that holds or passes a data signal input on the basis of a first clock signal (C_dly, CN_dly), a slave latch unit (16, 60) that holds or passes the data signal received from the master latch unit (54, 14) in a complementary manner with the master latch unit (54, 14)) on the basis of the second clock signal (C, CN), and a transmission period variable unit (26, 12) that varies the period through which the data signal passes in the master latch unit (54, 14).SELECTED DRAWING: Figure 1
【課題】より高速化が可能なフリップフロップ回路を備えた半導体集積回路を提供すること。【解決手段】第１のクロック信号（Ｃ＿ｄｌｙ、ＣＮ＿ｄｌｙ）に基づいて入力されたデータ信号を保持またはスルーするマスタラッチ部（５４、１４）と、第２のクロック信号（Ｃ、ＣＮ）に基づいて、マスタラッチ部（５４、１４）から受け取ったデータ信号をマスタラッチ部（５４、１４）とは相補的に保持またはスルーするスレーブラッチ部（１６、６０）と、マスタラッチ部（５４、１４）においてデータ信号のスルーする期間を可変とする透過期間可変部（２６、１２）と、を含む。【選択図】図１</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhpaGFmYWpiaOxkQpAgBU5iKs</recordid><startdate>20191024</startdate><enddate>20191024</enddate><creator>GOTO KAZUAKI</creator><scope>EVB</scope></search><sort><creationdate>20191024</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>GOTO KAZUAKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019186854A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>GOTO KAZUAKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GOTO KAZUAKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>2019-10-24</date><risdate>2019</risdate><abstract>To provide a semiconductor integrated circuit equipped with a flip-flop circuit capable of higher speed.SOLUTION: A semiconductor integrated circuit includes a master latch unit (54, 14) that holds or passes a data signal input on the basis of a first clock signal (C_dly, CN_dly), a slave latch unit (16, 60) that holds or passes the data signal received from the master latch unit (54, 14) in a complementary manner with the master latch unit (54, 14)) on the basis of the second clock signal (C, CN), and a transmission period variable unit (26, 12) that varies the period through which the data signal passes in the master latch unit (54, 14).SELECTED DRAWING: Figure 1
【課題】より高速化が可能なフリップフロップ回路を備えた半導体集積回路を提供すること。【解決手段】第１のクロック信号（Ｃ＿ｄｌｙ、ＣＮ＿ｄｌｙ）に基づいて入力されたデータ信号を保持またはスルーするマスタラッチ部（５４、１４）と、第２のクロック信号（Ｃ、ＣＮ）に基づいて、マスタラッチ部（５４、１４）から受け取ったデータ信号をマスタラッチ部（５４、１４）とは相補的に保持またはスルーするスレーブラッチ部（１６、６０）と、マスタラッチ部（５４、１４）においてデータ信号のスルーする期間を可変とする透過期間可変部（２６、１２）と、を含む。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| title | SEMICONDUCTOR INTEGRATED CIRCUIT |
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