SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To suppress a member arranged at a circumference of a bottom part of a side face of a contact hole from eroding while suppressing contact resistance from increasing.SOLUTION: A semiconductor device 100 comprises: a first step part 2A arranged on a first surface 1A of a substrate 1; a first barrier f...

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1. Verfasser:	SANO KAZUYA
Format:	Patent
Sprache:	eng ; jpn
Schlagworte:	BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY SEMICONDUCTOR DEVICES SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION
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creator	SANO KAZUYA
description	To suppress a member arranged at a circumference of a bottom part of a side face of a contact hole from eroding while suppressing contact resistance from increasing.SOLUTION: A semiconductor device 100 comprises: a first step part 2A arranged on a first surface 1A of a substrate 1; a first barrier film 3 arranged to cover the first step part 2A; and a first insulation film 4 arranged on the first barrier film 3. The first barrier film 3 and first insulation film 4 have contact holes 3H, 4H, reaching the first surface 1A, arranged where they do not overlap with the first step part 2A in plane view. The semiconductor device 100 further comprises: a second barrier film 5 arranged to cover surfaces of the contact holes 3H, 4H, and a contact part 6 arranged on the second barrier film 5 in the contact holes 3H, 4H. The first barrier film 3 has a first part 3A in contact with the second barrier film 5 at bottom parts of side faces of the surfaces of the contact holes 3H, 4H.SELECTED DRAWING: Figure 1 【課題】コンタクト抵抗の増加を抑制しつつ、コンタクトホールの側面の底部の周囲に配置された部材の侵食が抑制する。【解決手段】半導体装置１００は、基板１の第１面１Ａ上に配置されている第１段差部２Ａと、第１段差部２Ａを覆うように配置されている第１バリア膜３と、第１バリア膜３上に配置されている第１絶縁膜４とを備える。第１バリア膜３および第１絶縁膜４には、平面視において第１段差部２Ａと重ならない位置に、第１面１Ａに達するコンタクトホール３Ｈ，４Ｈが配置されている。上記半導体装置１００は、コンタクトホール３Ｈ，４Ｈの表面を覆うように配置されている第２バリア膜５と、コンタクトホール３Ｈ，４Ｈ内において第２バリア膜５上に配置されているコンタクト部６とをさらに備える。第１バリア膜３は、コンタクトホール３Ｈ，４Ｈの表面のうちの側面の底部において第１部３Ａは、第２バリア膜５に接している。【選択図】図１
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The first barrier film 3 and first insulation film 4 have contact holes 3H, 4H, reaching the first surface 1A, arranged where they do not overlap with the first step part 2A in plane view. The semiconductor device 100 further comprises: a second barrier film 5 arranged to cover surfaces of the contact holes 3H, 4H, and a contact part 6 arranged on the second barrier film 5 in the contact holes 3H, 4H. The first barrier film 3 has a first part 3A in contact with the second barrier film 5 at bottom parts of side faces of the surfaces of the contact holes 3H, 4H.SELECTED DRAWING: Figure 1 【課題】コンタクト抵抗の増加を抑制しつつ、コンタクトホールの側面の底部の周囲に配置された部材の侵食が抑制する。【解決手段】半導体装置１００は、基板１の第１面１Ａ上に配置されている第１段差部２Ａと、第１段差部２Ａを覆うように配置されている第１バリア膜３と、第１バリア膜３上に配置されている第１絶縁膜４とを備える。第１バリア膜３および第１絶縁膜４には、平面視において第１段差部２Ａと重ならない位置に、第１面１Ａに達するコンタクトホール３Ｈ，４Ｈが配置されている。上記半導体装置１００は、コンタクトホール３Ｈ，４Ｈの表面を覆うように配置されている第２バリア膜５と、コンタクトホール３Ｈ，４Ｈ内において第２バリア膜５上に配置されているコンタクト部６とをさらに備える。第１バリア膜３は、コンタクトホール３Ｈ，４Ｈの表面のうちの側面の底部において第１部３Ａは、第２バリア膜５に接している。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CHEMICAL SURFACE TREATMENT ; CHEMISTRY ; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL ; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL ; COATING MATERIAL WITH METALLIC MATERIAL ; COATING METALLIC MATERIAL ; DIFFUSION TREATMENT OF METALLIC MATERIAL ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL ; METALLURGY ; SEMICONDUCTOR DEVICES ; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190725&DB=EPODOC&CC=JP&NR=2019125754A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190725&DB=EPODOC&CC=JP&NR=2019125754A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SANO KAZUYA</creatorcontrib><title>SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME</title><description>To suppress a member arranged at a circumference of a bottom part of a side face of a contact hole from eroding while suppressing contact resistance from increasing.SOLUTION: A semiconductor device 100 comprises: a first step part 2A arranged on a first surface 1A of a substrate 1; a first barrier film 3 arranged to cover the first step part 2A; and a first insulation film 4 arranged on the first barrier film 3. The first barrier film 3 and first insulation film 4 have contact holes 3H, 4H, reaching the first surface 1A, arranged where they do not overlap with the first step part 2A in plane view. The semiconductor device 100 further comprises: a second barrier film 5 arranged to cover surfaces of the contact holes 3H, 4H, and a contact part 6 arranged on the second barrier film 5 in the contact holes 3H, 4H. The first barrier film 3 has a first part 3A in contact with the second barrier film 5 at bottom parts of side faces of the surfaces of the contact holes 3H, 4H.SELECTED DRAWING: Figure 1 【課題】コンタクト抵抗の増加を抑制しつつ、コンタクトホールの側面の底部の周囲に配置された部材の侵食が抑制する。【解決手段】半導体装置１００は、基板１の第１面１Ａ上に配置されている第１段差部２Ａと、第１段差部２Ａを覆うように配置されている第１バリア膜３と、第１バリア膜３上に配置されている第１絶縁膜４とを備える。第１バリア膜３および第１絶縁膜４には、平面視において第１段差部２Ａと重ならない位置に、第１面１Ａに達するコンタクトホール３Ｈ，４Ｈが配置されている。上記半導体装置１００は、コンタクトホール３Ｈ，４Ｈの表面を覆うように配置されている第２バリア膜５と、コンタクトホール３Ｈ，４Ｈ内において第２バリア膜５上に配置されているコンタクト部６とをさらに備える。第１バリア膜３は、コンタクトホール３Ｈ，４Ｈの表面のうちの側面の底部において第１部３Ａは、第２バリア膜５に接している。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CHEMICAL SURFACE TREATMENT</subject><subject>CHEMISTRY</subject><subject>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</subject><subject>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</subject><subject>COATING MATERIAL WITH METALLIC MATERIAL</subject><subject>COATING METALLIC MATERIAL</subject><subject>DIFFUSION TREATMENT OF METALLIC MATERIAL</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL</subject><subject>METALLURGY</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAMdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UfB3U_B19At1c3QOCQ3y9HNXCPFwVQh29HXlYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoaWhkam5qYmjsZEKQIAzzkpDw</recordid><startdate>20190725</startdate><enddate>20190725</enddate><creator>SANO KAZUYA</creator><scope>EVB</scope></search><sort><creationdate>20190725</creationdate><title>SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME</title><author>SANO KAZUYA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019125754A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CHEMICAL SURFACE TREATMENT</topic><topic>CHEMISTRY</topic><topic>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</topic><topic>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</topic><topic>COATING MATERIAL WITH METALLIC MATERIAL</topic><topic>COATING METALLIC MATERIAL</topic><topic>DIFFUSION TREATMENT OF METALLIC MATERIAL</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL</topic><topic>METALLURGY</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION</topic><toplevel>online_resources</toplevel><creatorcontrib>SANO KAZUYA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SANO KAZUYA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME</title><date>2019-07-25</date><risdate>2019</risdate><abstract>To suppress a member arranged at a circumference of a bottom part of a side face of a contact hole from eroding while suppressing contact resistance from increasing.SOLUTION: A semiconductor device 100 comprises: a first step part 2A arranged on a first surface 1A of a substrate 1; a first barrier film 3 arranged to cover the first step part 2A; and a first insulation film 4 arranged on the first barrier film 3. The first barrier film 3 and first insulation film 4 have contact holes 3H, 4H, reaching the first surface 1A, arranged where they do not overlap with the first step part 2A in plane view. The semiconductor device 100 further comprises: a second barrier film 5 arranged to cover surfaces of the contact holes 3H, 4H, and a contact part 6 arranged on the second barrier film 5 in the contact holes 3H, 4H. The first barrier film 3 has a first part 3A in contact with the second barrier film 5 at bottom parts of side faces of the surfaces of the contact holes 3H, 4H.SELECTED DRAWING: Figure 1 【課題】コンタクト抵抗の増加を抑制しつつ、コンタクトホールの側面の底部の周囲に配置された部材の侵食が抑制する。【解決手段】半導体装置１００は、基板１の第１面１Ａ上に配置されている第１段差部２Ａと、第１段差部２Ａを覆うように配置されている第１バリア膜３と、第１バリア膜３上に配置されている第１絶縁膜４とを備える。第１バリア膜３および第１絶縁膜４には、平面視において第１段差部２Ａと重ならない位置に、第１面１Ａに達するコンタクトホール３Ｈ，４Ｈが配置されている。上記半導体装置１００は、コンタクトホール３Ｈ，４Ｈの表面を覆うように配置されている第２バリア膜５と、コンタクトホール３Ｈ，４Ｈ内において第２バリア膜５上に配置されているコンタクト部６とをさらに備える。第１バリア膜３は、コンタクトホール３Ｈ，４Ｈの表面のうちの側面の底部において第１部３Ａは、第２バリア膜５に接している。【選択図】図１</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY SEMICONDUCTOR DEVICES SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION
title	SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
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