METHOD FOR MANUFACTURING LAMINATE WAFER, AND LAMINATE WAFER

To provide: a method for manufacturing a laminate wafer, by which a polycrystalline silicon layer small in the variation in thickness, less in fine defects and high in flatness can be obtained; and a laminate wafer having a polycrystalline silicon layer small in the variation in thickness, less in fine defects, and high in flatness.SOLUTION: In a method for manufacturing a laminate wafer according to the present invention, the sinking quantity of a polishing cloth is 50 to 90 μm. The polishing cloth has a surface hardness (ASKER C) of 50-60. The laminate wafer of the invention comprises a polycrystalline silicon wafer layer of which the variation Δt in thickness is 5% or less. A wafer for a support substrate after polishing the polycrystalline silicon wafer layer is 0.2 μm or less in GBIR, and 0.06 μm or less in SFQR.SELECTED DRAWING: Figure 2 【課題】本発明は、厚さのばらつきが小さく、微小欠陥が少なく、平坦性が高い多結晶シリコン層を得ることのできる、貼り合わせウェーハの製造方法、及び、厚さのばらつきが小さく、微小欠陥が少なく、平坦性が高い多結晶シリコン層を有する、貼り合わせウェーハを提供することを目的とする。【解決手段】本発明の貼り合わせウェーハの製造方法は、研磨布の沈み込み量は、５０〜９０μｍであり、且つ、前記研磨布の表面硬度（ＡＳＫＥＲ Ｃ）は、５０〜６０である。本発明の貼り合わせウェーハは、多結晶シリコンウェーハ層は、厚さのばらつきΔｔが５％以下であり、前記多結晶シリコンウェーハ層を研磨した後の、支持基板用ウェーハは、ＧＢＩＲが０．２μｍ以下、ＳＦＱＲが０．０６μｍ以下である。【選択図】図２