GATE DRIVE CIRCUIT

To further reduce leakage inductance to shorten a gate rise time while reducing coupling capacitance between winding in a pulse width modulation type pulse power supply.SOLUTION: A pulse transformer type gate drive circuit 1 in a pulse power supply comprises: a substrate 10 of a gate drive circuit 1...

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Hauptverfasser:	AZUMA MASAO, OSADA TOSHIHIRO
Format:	Patent
Sprache:	eng ; jpn
Schlagworte:	APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS CONTROL OR REGULATION THEREOF CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY GENERATION
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creator	AZUMA MASAO OSADA TOSHIHIRO
description	To further reduce leakage inductance to shorten a gate rise time while reducing coupling capacitance between winding in a pulse width modulation type pulse power supply.SOLUTION: A pulse transformer type gate drive circuit 1 in a pulse power supply comprises: a substrate 10 of a gate drive circuit 1 that is serially implemented in plural in the pulse power supply; a core 13 that is implemented on the substrate 10 and into which a primary winding 11 of a pulse transformer is inserted; and a secondary winding 12 of the pulse transformer that is implemented on the substrate 10 and is wound about the core 13 with an element wire being loosen into a plurality of bundles.SELECTED DRAWING: Figure 1 【課題】パルス幅変調式パルス電源において、巻線間の結合容量を低減しつつ、漏れインダクタンスをより低減させて、ゲート立ち上がり時間の短縮を図る。【解決手段】パルス電源におけるパルストランス方式のゲート駆動回路１であって、パルス電源に複数直列に実装されるゲート駆動回路１の基板１０と、この基板１０に実装される一方でパルストランスの一次側電線１１が挿通されるコア１３と、前記基板１０に実装される一方で素線が複数の束にほぐされた状態でコア１３に巻線される前記パルストランスの二次側電線１２とを備える。【選択図】図１
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a core 13 that is implemented on the substrate 10 and into which a primary winding 11 of a pulse transformer is inserted; and a secondary winding 12 of the pulse transformer that is implemented on the substrate 10 and is wound about the core 13 with an element wire being loosen into a plurality of bundles.SELECTED DRAWING: Figure 1 【課題】パルス幅変調式パルス電源において、巻線間の結合容量を低減しつつ、漏れインダクタンスをより低減させて、ゲート立ち上がり時間の短縮を図る。【解決手段】パルス電源におけるパルストランス方式のゲート駆動回路１であって、パルス電源に複数直列に実装されるゲート駆動回路１の基板１０と、この基板１０に実装される一方でパルストランスの一次側電線１１が挿通されるコア１３と、前記基板１０に実装される一方で素線が複数の束にほぐされた状態でコア１３に巻線される前記パルストランスの二次側電線１２とを備える。【選択図】図１</description><language>eng ; jpn</language><subject>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS ; CONTROL OR REGULATION THEREOF ; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER ; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRICITY ; GENERATION</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190627&DB=EPODOC&CC=JP&NR=2019106802A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190627&DB=EPODOC&CC=JP&NR=2019106802A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AZUMA MASAO</creatorcontrib><creatorcontrib>OSADA TOSHIHIRO</creatorcontrib><title>GATE DRIVE CIRCUIT</title><description>To further reduce leakage inductance to shorten a gate rise time while reducing coupling capacitance between winding in a pulse width modulation type pulse power supply.SOLUTION: A pulse transformer type gate drive circuit 1 in a pulse power supply comprises: a substrate 10 of a gate drive circuit 1 that is serially implemented in plural in the pulse power supply; a core 13 that is implemented on the substrate 10 and into which a primary winding 11 of a pulse transformer is inserted; and a secondary winding 12 of the pulse transformer that is implemented on the substrate 10 and is wound about the core 13 with an element wire being loosen into a plurality of bundles.SELECTED DRAWING: Figure 1 【課題】パルス幅変調式パルス電源において、巻線間の結合容量を低減しつつ、漏れインダクタンスをより低減させて、ゲート立ち上がり時間の短縮を図る。【解決手段】パルス電源におけるパルストランス方式のゲート駆動回路１であって、パルス電源に複数直列に実装されるゲート駆動回路１の基板１０と、この基板１０に実装される一方でパルストランスの一次側電線１１が挿通されるコア１３と、前記基板１０に実装される一方で素線が複数の束にほぐされた状態でコア１３に巻線される前記パルストランスの二次側電線１２とを備える。【選択図】図１</description><subject>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS</subject><subject>CONTROL OR REGULATION THEREOF</subject><subject>CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRICITY</subject><subject>GENERATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBBydwxxVXAJ8gxzVXD2DHIO9QzhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoaWhgZmFgZGjsZEKQIAaQ8eVQ</recordid><startdate>20190627</startdate><enddate>20190627</enddate><creator>AZUMA MASAO</creator><creator>OSADA TOSHIHIRO</creator><scope>EVB</scope></search><sort><creationdate>20190627</creationdate><title>GATE DRIVE CIRCUIT</title><author>AZUMA MASAO ; OSADA TOSHIHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019106802A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS</topic><topic>CONTROL OR REGULATION THEREOF</topic><topic>CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRICITY</topic><topic>GENERATION</topic><toplevel>online_resources</toplevel><creatorcontrib>AZUMA MASAO</creatorcontrib><creatorcontrib>OSADA TOSHIHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AZUMA MASAO</au><au>OSADA TOSHIHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>GATE DRIVE CIRCUIT</title><date>2019-06-27</date><risdate>2019</risdate><abstract>To further reduce leakage inductance to shorten a gate rise time while reducing coupling capacitance between winding in a pulse width modulation type pulse power supply.SOLUTION: A pulse transformer type gate drive circuit 1 in a pulse power supply comprises: a substrate 10 of a gate drive circuit 1 that is serially implemented in plural in the pulse power supply; a core 13 that is implemented on the substrate 10 and into which a primary winding 11 of a pulse transformer is inserted; and a secondary winding 12 of the pulse transformer that is implemented on the substrate 10 and is wound about the core 13 with an element wire being loosen into a plurality of bundles.SELECTED DRAWING: Figure 1 【課題】パルス幅変調式パルス電源において、巻線間の結合容量を低減しつつ、漏れインダクタンスをより低減させて、ゲート立ち上がり時間の短縮を図る。【解決手段】パルス電源におけるパルストランス方式のゲート駆動回路１であって、パルス電源に複数直列に実装されるゲート駆動回路１の基板１０と、この基板１０に実装される一方でパルストランスの一次側電線１１が挿通されるコア１３と、前記基板１０に実装される一方で素線が複数の束にほぐされた状態でコア１３に巻線される前記パルストランスの二次側電線１２とを備える。【選択図】図１</abstract><oa>free_for_read</oa></addata></record>
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subjects	APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS CONTROL OR REGULATION THEREOF CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY GENERATION
title	GATE DRIVE CIRCUIT
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