SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

To provide a stacked CMOS where an upper-layer surrounding gate electrode acts as a lower-layer gate electrode.SOLUTION: A CMOS composed of stacked P-channel and N-channel MIS field effect transistors comprises: lower semiconductor layers (2, 12) provided on a semiconductor substrate 1; upper semiconductor layers (9, 11, 13) provided on the lower semiconductor layers via an interlayer insulation film 7; a surrounding gate electrode 16 including a lower-layer gate electrode, which has a structure of surrounding all round a part 13 of the upper semiconductor layers via an upper-layer gate insulation film 15 and provided directly on a part 12 of the lower semiconductor layers via a lower-layer gate insulation film 14; and one conductivity type source-drain regions (5, 6) provided in a part 2 of the lower semiconductor layers and the opposite conductivity type source-drain regions (17-20) provided parts (9, 11) of the upper semiconductor layers, which have a structure with opposite ends forming perpendicular planes with respect to a principal surface of the semiconductor substrate in a self-aligned fashion with the surrounding gate electrode 16.SELECTED DRAWING: Figure 1 【課題】上層包囲型ゲート電極で、下層ゲート電極を代行した積層ＣＭＯＳの提供【解決手段】半導体基板１上に下層半導体層（２、１２）が設けられ、下層半導体層上に層間絶縁膜７を介して上層半導体層（９、１１、１３）が設けられ、上層半導体層の一部１３の全周囲に上層ゲート絶縁膜１５を介して包囲する構造の、下層ゲート電極を含む包囲型ゲート電極１６が、下層半導体層の一部１２直上に下層ゲート絶縁膜１４を介して設けられ、包囲型ゲート電極１６に自己整合して、対向する端部が半導体基板の主面に垂直平面をなす構造の、一導電型ソースドレイン領域（５、６）を下層半導体層の一部２に、反対導電型ソースドレイン領域（１７〜２０）を上層半導体層の一部（９、１１）に設けた積層構造のＰチャネル及びＮチャネルのＭＩＳ電界効果トランジスタからなるＣＭＯＳ。【選択図】図１