DC-DC CONVERTER
To reduce the loss of a DC-DC converter.SOLUTION: In a DC-DC converter 10, a plurality of series circuits comprising a series circuit of a lower FET 31 and an upper FET 32 and a series circuit of a lower FET 33 and an upper FET 34 are connected in parallel between high-potential output wiring 14 and...
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| creator | TOGYO KEN OKAMURA SAKAKI |
| description | To reduce the loss of a DC-DC converter.SOLUTION: In a DC-DC converter 10, a plurality of series circuits comprising a series circuit of a lower FET 31 and an upper FET 32 and a series circuit of a lower FET 33 and an upper FET 34 are connected in parallel between high-potential output wiring 14 and low-potential output wiring 16. Diodes 42, 44 are connected in parallel to the upper FETs 32, 34, respectively. A main reactor 22 is connected to high-potential input wiring 12, a first sub reactor 24 is connected between the main reactor and the first lower FET 31, and a second sub reactor 26 is connected between the main reactor and the second lower FET 33. A gate control unit 54 has control means that does not turn on the upper FETs 32, 34 in a zero cross mode that has a period in which current flowing through the main reactor is zero.SELECTED DRAWING: Figure 1
【課題】ＤＣ−ＤＣコンバータの損失を低減する。【解決手段】ＤＣ−ＤＣコンバータ１０には、高電位出力配線１４と低電位配線１６の間に、下側ＦＥＴ３１、３３と上側ＦＥＴ３２、３４の直列回路が複数個並列に接続されている。各上側ＦＥＴに対してダイオード４２、４４が並列接続されている。高電位入力配線１２にメインリアクトル２２が接続されており、メインリアクトルと第１下側ＦＥＴ３１の間に第１サブリアクトル２４が接続されており、メインリアクトルと第２下側ＦＥＴ３３の間に第２サブリアクトル２６が接続されている。ゲート制御装置５４は、メインリアクトルに流れる電流がゼロになる期間を有するゼロクロスモードにおいて、上側ＦＥＴ３２、３４をオンさせない制御手段を有する。【選択図】図１ |
| format | Patent |
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【課題】ＤＣ−ＤＣコンバータの損失を低減する。【解決手段】ＤＣ−ＤＣコンバータ１０には、高電位出力配線１４と低電位配線１６の間に、下側ＦＥＴ３１、３３と上側ＦＥＴ３２、３４の直列回路が複数個並列に接続されている。各上側ＦＥＴに対してダイオード４２、４４が並列接続されている。高電位入力配線１２にメインリアクトル２２が接続されており、メインリアクトルと第１下側ＦＥＴ３１の間に第１サブリアクトル２４が接続されており、メインリアクトルと第２下側ＦＥＴ３３の間に第２サブリアクトル２６が接続されている。ゲート制御装置５４は、メインリアクトルに流れる電流がゼロになる期間を有するゼロクロスモードにおいて、上側ＦＥＴ３２、３４をオンさせない制御手段を有する。【選択図】図１</description><language>eng ; jpn</language><subject>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS ; CONTROL OR REGULATION THEREOF ; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER ; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRICITY ; GENERATION</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190411&DB=EPODOC&CC=JP&NR=2019057991A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190411&DB=EPODOC&CC=JP&NR=2019057991A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TOGYO KEN</creatorcontrib><creatorcontrib>OKAMURA SAKAKI</creatorcontrib><title>DC-DC CONVERTER</title><description>To reduce the loss of a DC-DC converter.SOLUTION: In a DC-DC converter 10, a plurality of series circuits comprising a series circuit of a lower FET 31 and an upper FET 32 and a series circuit of a lower FET 33 and an upper FET 34 are connected in parallel between high-potential output wiring 14 and low-potential output wiring 16. Diodes 42, 44 are connected in parallel to the upper FETs 32, 34, respectively. A main reactor 22 is connected to high-potential input wiring 12, a first sub reactor 24 is connected between the main reactor and the first lower FET 31, and a second sub reactor 26 is connected between the main reactor and the second lower FET 33. A gate control unit 54 has control means that does not turn on the upper FETs 32, 34 in a zero cross mode that has a period in which current flowing through the main reactor is zero.SELECTED DRAWING: Figure 1
【課題】ＤＣ−ＤＣコンバータの損失を低減する。【解決手段】ＤＣ−ＤＣコンバータ１０には、高電位出力配線１４と低電位配線１６の間に、下側ＦＥＴ３１、３３と上側ＦＥＴ３２、３４の直列回路が複数個並列に接続されている。各上側ＦＥＴに対してダイオード４２、４４が並列接続されている。高電位入力配線１２にメインリアクトル２２が接続されており、メインリアクトルと第１下側ＦＥＴ３１の間に第１サブリアクトル２４が接続されており、メインリアクトルと第２下側ＦＥＴ３３の間に第２サブリアクトル２６が接続されている。ゲート制御装置５４は、メインリアクトルに流れる電流がゼロになる期間を有するゼロクロスモードにおいて、上側ＦＥＴ３２、３４をオンさせない制御手段を有する。【選択図】図１</description><subject>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS</subject><subject>CONTROL OR REGULATION THEREOF</subject><subject>CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRICITY</subject><subject>GENERATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOB3cdZ1cVZw9vcLcw0KcQ3iYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoaWBqbmlpaGjsZEKQIADh0dkw</recordid><startdate>20190411</startdate><enddate>20190411</enddate><creator>TOGYO KEN</creator><creator>OKAMURA SAKAKI</creator><scope>EVB</scope></search><sort><creationdate>20190411</creationdate><title>DC-DC CONVERTER</title><author>TOGYO KEN ; OKAMURA SAKAKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019057991A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS</topic><topic>CONTROL OR REGULATION THEREOF</topic><topic>CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRICITY</topic><topic>GENERATION</topic><toplevel>online_resources</toplevel><creatorcontrib>TOGYO KEN</creatorcontrib><creatorcontrib>OKAMURA SAKAKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TOGYO KEN</au><au>OKAMURA SAKAKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DC-DC CONVERTER</title><date>2019-04-11</date><risdate>2019</risdate><abstract>To reduce the loss of a DC-DC converter.SOLUTION: In a DC-DC converter 10, a plurality of series circuits comprising a series circuit of a lower FET 31 and an upper FET 32 and a series circuit of a lower FET 33 and an upper FET 34 are connected in parallel between high-potential output wiring 14 and low-potential output wiring 16. Diodes 42, 44 are connected in parallel to the upper FETs 32, 34, respectively. A main reactor 22 is connected to high-potential input wiring 12, a first sub reactor 24 is connected between the main reactor and the first lower FET 31, and a second sub reactor 26 is connected between the main reactor and the second lower FET 33. A gate control unit 54 has control means that does not turn on the upper FETs 32, 34 in a zero cross mode that has a period in which current flowing through the main reactor is zero.SELECTED DRAWING: Figure 1
【課題】ＤＣ−ＤＣコンバータの損失を低減する。【解決手段】ＤＣ−ＤＣコンバータ１０には、高電位出力配線１４と低電位配線１６の間に、下側ＦＥＴ３１、３３と上側ＦＥＴ３２、３４の直列回路が複数個並列に接続されている。各上側ＦＥＴに対してダイオード４２、４４が並列接続されている。高電位入力配線１２にメインリアクトル２２が接続されており、メインリアクトルと第１下側ＦＥＴ３１の間に第１サブリアクトル２４が接続されており、メインリアクトルと第２下側ＦＥＴ３３の間に第２サブリアクトル２６が接続されている。ゲート制御装置５４は、メインリアクトルに流れる電流がゼロになる期間を有するゼロクロスモードにおいて、上側ＦＥＴ３２、３４をオンさせない制御手段を有する。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS CONTROL OR REGULATION THEREOF CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY GENERATION |
| title | DC-DC CONVERTER |
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