SEMICONDUCTOR DEVICE

To provide a semiconductor device that has a stable drain current in a saturation region of a transistor.SOLUTION: A semiconductor device comprises: a semiconductor part of a first conductivity type; a first semiconductor layer and a second semiconductor layer of a second conductivity type that are...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: NISHIGORI MASATO, FUKAI YASUSHI, KITAHARA HIROYOSHI, TERADA NAOZUMI
Format: Patent
Sprache:eng ; jpn
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Beschreibung
Zusammenfassung:To provide a semiconductor device that has a stable drain current in a saturation region of a transistor.SOLUTION: A semiconductor device comprises: a semiconductor part of a first conductivity type; a first semiconductor layer and a second semiconductor layer of a second conductivity type that are provided at an upper layer part of the semiconductor part so as to be separated from each other; a gate electrode provided on the semiconductor part; a first contact penetrating through the gate electrode, and whose lower part is arranged in the first semiconductor layer, and whose lower end is connected with the first semiconductor layer; a second contact penetrating through the gate electrode, and whose lower part is arranged in the second semiconductor layer, and whose lower end is connected with the second semiconductor layer; a first insulating film provided between a lateral face of the first contact and the first semiconductor layer and between the first contact and the gate electrode; and a second insulating film provided between a lateral face of the second contact and the second semiconductor layer and between the second contact and the gate electrode.SELECTED DRAWING: Figure 1 【課題】トランジスタの飽和領域において、ドレイン電流が安定な半導体装置を提供する。【解決手段】半導体装置は、第1導電形の半導体部分と、前記半導体部分の上層部分に相互に離隔して設けられた第2導電形の第1半導体層及び第2半導体層と、前記半導体部分上に設けられたゲート電極と、前記ゲート電極を貫通し、下部が前記第1半導体層内に配置され、下端が前記第1半導体層に接続された第1コンタクトと、前記ゲート電極を貫通し、下部が前記第2半導体層内に配置され、下端が前記第2半導体層に接続された第2コンタクトと、前記第1コンタクトの側面と前記第1半導体層との間、及び、前記第1コンタクトと前記ゲート電極との間に設けられた第1絶縁膜と、前記第2コンタクトの側面と前記第2半導体層との間、及び、前記第2コンタクトと前記ゲート電極との間に設けられた第2絶縁膜と、を備える。【選択図】図1