SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME, AND INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
To provide a semiconductor chip that enables high speed and high integration, and to provide a method of manufacturing the same, and an integrated circuit device and a method of manufacturing the same.SOLUTION: An integrated circuit device 1 comprises: a support substrate 11; a first semiconductor c...
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| creator | KIMIZUKA AKIRA CHORI KANJI YAMAMOTO TAKESHI INODO HIDEKAZU HABU MARIKO |
| description | To provide a semiconductor chip that enables high speed and high integration, and to provide a method of manufacturing the same, and an integrated circuit device and a method of manufacturing the same.SOLUTION: An integrated circuit device 1 comprises: a support substrate 11; a first semiconductor chip 10A and a second semiconductor chip 10B provided on the support substrate; and a connection member 12 formed of a solder. Each of the first semiconductor chip and the second semiconductor chip has a semiconductor substrate, a wiring layer 21 provided on the semiconductor substrate, and a pad 40 provided on a lateral face of the wiring layer. The connection member is contacted with a lateral face of a pad of the first semiconductor chip and a lateral face 40b of a pad of the second semiconductor chip.SELECTED DRAWING: Figure 2
【課題】高速化及び高集積化が可能な半導体チップ及びその製造方法、並びに、集積回路装置及びその製造方法を提供する。【解決手段】集積回路装置１は、支持基板１１と、支持基板上に設けられた第１半導体チップ１０Ａ及び第２半導体チップ１０Ｂと、半田からなる接続部材１２と、を備える。第１半導体チップ及び前記第２半導体チップは、それぞれ、半導体基板と、半導体基板上に設けられた配線層２１と、配線層の側面上に設けられたパッド４０と、を有する。接続部材は、第１半導体チップのパッドの側面と、第２半導体チップのパッドの側面４０ｂに接している。【選択図】図２ |
| format | Patent |
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【課題】高速化及び高集積化が可能な半導体チップ及びその製造方法、並びに、集積回路装置及びその製造方法を提供する。【解決手段】集積回路装置１は、支持基板１１と、支持基板上に設けられた第１半導体チップ１０Ａ及び第２半導体チップ１０Ｂと、半田からなる接続部材１２と、を備える。第１半導体チップ及び前記第２半導体チップは、それぞれ、半導体基板と、半導体基板上に設けられた配線層２１と、配線層の側面上に設けられたパッド４０と、を有する。接続部材は、第１半導体チップのパッドの側面と、第２半導体チップのパッドの側面４０ｂに接している。【選択図】図２</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190404&DB=EPODOC&CC=JP&NR=2019054155A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190404&DB=EPODOC&CC=JP&NR=2019054155A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIMIZUKA AKIRA</creatorcontrib><creatorcontrib>CHORI KANJI</creatorcontrib><creatorcontrib>YAMAMOTO TAKESHI</creatorcontrib><creatorcontrib>INODO HIDEKAZU</creatorcontrib><creatorcontrib>HABU MARIKO</creatorcontrib><title>SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME, AND INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME</title><description>To provide a semiconductor chip that enables high speed and high integration, and to provide a method of manufacturing the same, and an integrated circuit device and a method of manufacturing the same.SOLUTION: An integrated circuit device 1 comprises: a support substrate 11; a first semiconductor chip 10A and a second semiconductor chip 10B provided on the support substrate; and a connection member 12 formed of a solder. Each of the first semiconductor chip and the second semiconductor chip has a semiconductor substrate, a wiring layer 21 provided on the semiconductor substrate, and a pad 40 provided on a lateral face of the wiring layer. The connection member is contacted with a lateral face of a pad of the first semiconductor chip and a lateral face 40b of a pad of the second semiconductor chip.SELECTED DRAWING: Figure 2
【課題】高速化及び高集積化が可能な半導体チップ及びその製造方法、並びに、集積回路装置及びその製造方法を提供する。【解決手段】集積回路装置１は、支持基板１１と、支持基板上に設けられた第１半導体チップ１０Ａ及び第２半導体チップ１０Ｂと、半田からなる接続部材１２と、を備える。第１半導体チップ及び前記第２半導体チップは、それぞれ、半導体基板と、半導体基板上に設けられた配線層２１と、配線層の側面上に設けられたパッド４０と、を有する。接続部材は、第１半導体チップのパッドの側面と、第２半導体チップのパッドの側面４０ｂに接している。【選択図】図２</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzLEKwjAQgOEuDqK-w-Gs0KoZHMPl2pyQpKQX11IkTqKFuvnygvgAnf7l418Wn44cY_AmoYQIaLkF7Q04EhsMhBqc9qnWKCmyb0AsQacd7X6KvVATtZAB5IiJBQxdGWnWY10s7sNjypt_V8W2JkG7z-Orz9M43PIzv_tLeyirc6lOlVL6OAt9AWvSOqo</recordid><startdate>20190404</startdate><enddate>20190404</enddate><creator>KIMIZUKA AKIRA</creator><creator>CHORI KANJI</creator><creator>YAMAMOTO TAKESHI</creator><creator>INODO HIDEKAZU</creator><creator>HABU MARIKO</creator><scope>EVB</scope></search><sort><creationdate>20190404</creationdate><title>SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME, AND INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME</title><author>KIMIZUKA AKIRA ; CHORI KANJI ; YAMAMOTO TAKESHI ; INODO HIDEKAZU ; HABU MARIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019054155A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIMIZUKA AKIRA</creatorcontrib><creatorcontrib>CHORI KANJI</creatorcontrib><creatorcontrib>YAMAMOTO TAKESHI</creatorcontrib><creatorcontrib>INODO HIDEKAZU</creatorcontrib><creatorcontrib>HABU MARIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIMIZUKA AKIRA</au><au>CHORI KANJI</au><au>YAMAMOTO TAKESHI</au><au>INODO HIDEKAZU</au><au>HABU MARIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME, AND INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME</title><date>2019-04-04</date><risdate>2019</risdate><abstract>To provide a semiconductor chip that enables high speed and high integration, and to provide a method of manufacturing the same, and an integrated circuit device and a method of manufacturing the same.SOLUTION: An integrated circuit device 1 comprises: a support substrate 11; a first semiconductor chip 10A and a second semiconductor chip 10B provided on the support substrate; and a connection member 12 formed of a solder. Each of the first semiconductor chip and the second semiconductor chip has a semiconductor substrate, a wiring layer 21 provided on the semiconductor substrate, and a pad 40 provided on a lateral face of the wiring layer. The connection member is contacted with a lateral face of a pad of the first semiconductor chip and a lateral face 40b of a pad of the second semiconductor chip.SELECTED DRAWING: Figure 2
【課題】高速化及び高集積化が可能な半導体チップ及びその製造方法、並びに、集積回路装置及びその製造方法を提供する。【解決手段】集積回路装置１は、支持基板１１と、支持基板上に設けられた第１半導体チップ１０Ａ及び第２半導体チップ１０Ｂと、半田からなる接続部材１２と、を備える。第１半導体チップ及び前記第２半導体チップは、それぞれ、半導体基板と、半導体基板上に設けられた配線層２１と、配線層の側面上に設けられたパッド４０と、を有する。接続部材は、第１半導体チップのパッドの側面と、第２半導体チップのパッドの側面４０ｂに接している。【選択図】図２</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME, AND INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME |
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