CONTROLLER DESIGN APPARATUS FOR ACOUSTIC SIGNAL, AND PROGRAM
To reduce gain of a controller by permitting reduction in control performance to some extent.SOLUTION: A controller design apparatus 1 comprises a control unit 10 including: an identification unit 20 for identifying a control object Gp and target system Gt; a delay time separation unit 21 for separa...
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creator | MATSUI KENTARO ITO ATSURO INOUE MASAKI ADACHI SHUICHI MORI SHOHEI |
description | To reduce gain of a controller by permitting reduction in control performance to some extent.SOLUTION: A controller design apparatus 1 comprises a control unit 10 including: an identification unit 20 for identifying a control object Gp and target system Gt; a delay time separation unit 21 for separating a delay time from the control object Gp to obtain a control object Gp# and separating a delay time from the target system Gt to obtain a target system Gt#; a system configuration unit 22 for configuring the whole system Hall by using a controller H0, the control object Gp#, the target system Gt#, a subtractor, and a balance coefficient α; a parameter determination unit 23 for varying the balance coefficient α and taking a H∞ norm of the whole system Hall as an evaluation function to determine coefficient matrices A0, B0, C0, D0 for the controller H0 to minimize the H∞ norm of the whole system Hall; and a delay time compensation unit 24 for calculating delay times Rd1 to Rdm2 for a delay device Rd and delayed times Rc1 to Rcm1 for a delay device Rc.SELECTED DRAWING: Figure 7
【課題】制御性能の低下をある程度許容することで、制御器のゲインを小さくする。【解決手段】制御器設計装置1に備えた制御部10の同定部20は、制御対象Gp及び目標システムGtを同定し、遅延時間分離部21は、制御対象Gpから遅延時間を分離して制御対象Gp#を求め、目標システムGtから遅延時間を分離して目標システムGt#を求める。システム構成部22は、制御器H0、制御対象Gp#、目標システムGt#、減算器及びバランス係数αを用いて、全体システムHallを構成する。パラメータ決定部23は、バランス係数αを変化させ、全体システムHallのH∞ノルムを評価関数として、全体システムHallのH∞ノルムを最小化する制御器H0の係数行列A0,B0,C0,D0を決定する。遅延時間補償部24は、遅延器Rdの遅延時間Rd1〜Rdm2及び遅延器Rcの遅延時間Rc1〜Rcm1を求める。【選択図】図7 |
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【課題】制御性能の低下をある程度許容することで、制御器のゲインを小さくする。【解決手段】制御器設計装置1に備えた制御部10の同定部20は、制御対象Gp及び目標システムGtを同定し、遅延時間分離部21は、制御対象Gpから遅延時間を分離して制御対象Gp#を求め、目標システムGtから遅延時間を分離して目標システムGt#を求める。システム構成部22は、制御器H0、制御対象Gp#、目標システムGt#、減算器及びバランス係数αを用いて、全体システムHallを構成する。パラメータ決定部23は、バランス係数αを変化させ、全体システムHallのH∞ノルムを評価関数として、全体システムHallのH∞ノルムを最小化する制御器H0の係数行列A0,B0,C0,D0を決定する。遅延時間補償部24は、遅延器Rdの遅延時間Rd1〜Rdm2及び遅延器Rcの遅延時間Rc1〜Rcm1を求める。【選択図】図7</description><language>eng ; jpn</language><subject>DEAF-AID SETS ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKEACOUSTIC ELECTROMECHANICAL TRANSDUCERS ; PUBLIC ADDRESS SYSTEMS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190322&DB=EPODOC&CC=JP&NR=2019047460A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190322&DB=EPODOC&CC=JP&NR=2019047460A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSUI KENTARO</creatorcontrib><creatorcontrib>ITO ATSURO</creatorcontrib><creatorcontrib>INOUE MASAKI</creatorcontrib><creatorcontrib>ADACHI SHUICHI</creatorcontrib><creatorcontrib>MORI SHOHEI</creatorcontrib><title>CONTROLLER DESIGN APPARATUS FOR ACOUSTIC SIGNAL, AND PROGRAM</title><description>To reduce gain of a controller by permitting reduction in control performance to some extent.SOLUTION: A controller design apparatus 1 comprises a control unit 10 including: an identification unit 20 for identifying a control object Gp and target system Gt; a delay time separation unit 21 for separating a delay time from the control object Gp to obtain a control object Gp# and separating a delay time from the target system Gt to obtain a target system Gt#; a system configuration unit 22 for configuring the whole system Hall by using a controller H0, the control object Gp#, the target system Gt#, a subtractor, and a balance coefficient α; a parameter determination unit 23 for varying the balance coefficient α and taking a H∞ norm of the whole system Hall as an evaluation function to determine coefficient matrices A0, B0, C0, D0 for the controller H0 to minimize the H∞ norm of the whole system Hall; and a delay time compensation unit 24 for calculating delay times Rd1 to Rdm2 for a delay device Rd and delayed times Rc1 to Rcm1 for a delay device Rc.SELECTED DRAWING: Figure 7
【課題】制御性能の低下をある程度許容することで、制御器のゲインを小さくする。【解決手段】制御器設計装置1に備えた制御部10の同定部20は、制御対象Gp及び目標システムGtを同定し、遅延時間分離部21は、制御対象Gpから遅延時間を分離して制御対象Gp#を求め、目標システムGtから遅延時間を分離して目標システムGt#を求める。システム構成部22は、制御器H0、制御対象Gp#、目標システムGt#、減算器及びバランス係数αを用いて、全体システムHallを構成する。パラメータ決定部23は、バランス係数αを変化させ、全体システムHallのH∞ノルムを評価関数として、全体システムHallのH∞ノルムを最小化する制御器H0の係数行列A0,B0,C0,D0を決定する。遅延時間補償部24は、遅延器Rdの遅延時間Rd1〜Rdm2及び遅延器Rcの遅延時間Rc1〜Rcm1を求める。【選択図】図7</description><subject>DEAF-AID SETS</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKEACOUSTIC ELECTROMECHANICAL TRANSDUCERS</subject><subject>PUBLIC ADDRESS SYSTEMS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBx9vcLCfL38XENUnBxDfZ091NwDAhwDHIMCQ1WcPMPUnB09g8NDvF0VgDJOfroKDj6uSgEBPm7Bzn68jCwpiXmFKfyQmluBiU31xBnD93Ugvz41OKCxOTUvNSSeK8AIwNDSwMTcxMzA0djohQBAF06Kf8</recordid><startdate>20190322</startdate><enddate>20190322</enddate><creator>MATSUI KENTARO</creator><creator>ITO ATSURO</creator><creator>INOUE MASAKI</creator><creator>ADACHI SHUICHI</creator><creator>MORI SHOHEI</creator><scope>EVB</scope></search><sort><creationdate>20190322</creationdate><title>CONTROLLER DESIGN APPARATUS FOR ACOUSTIC SIGNAL, AND PROGRAM</title><author>MATSUI KENTARO ; ITO ATSURO ; INOUE MASAKI ; ADACHI SHUICHI ; MORI SHOHEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2019047460A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2019</creationdate><topic>DEAF-AID SETS</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKEACOUSTIC ELECTROMECHANICAL TRANSDUCERS</topic><topic>PUBLIC ADDRESS SYSTEMS</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSUI KENTARO</creatorcontrib><creatorcontrib>ITO ATSURO</creatorcontrib><creatorcontrib>INOUE MASAKI</creatorcontrib><creatorcontrib>ADACHI SHUICHI</creatorcontrib><creatorcontrib>MORI SHOHEI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSUI KENTARO</au><au>ITO ATSURO</au><au>INOUE MASAKI</au><au>ADACHI SHUICHI</au><au>MORI SHOHEI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONTROLLER DESIGN APPARATUS FOR ACOUSTIC SIGNAL, AND PROGRAM</title><date>2019-03-22</date><risdate>2019</risdate><abstract>To reduce gain of a controller by permitting reduction in control performance to some extent.SOLUTION: A controller design apparatus 1 comprises a control unit 10 including: an identification unit 20 for identifying a control object Gp and target system Gt; a delay time separation unit 21 for separating a delay time from the control object Gp to obtain a control object Gp# and separating a delay time from the target system Gt to obtain a target system Gt#; a system configuration unit 22 for configuring the whole system Hall by using a controller H0, the control object Gp#, the target system Gt#, a subtractor, and a balance coefficient α; a parameter determination unit 23 for varying the balance coefficient α and taking a H∞ norm of the whole system Hall as an evaluation function to determine coefficient matrices A0, B0, C0, D0 for the controller H0 to minimize the H∞ norm of the whole system Hall; and a delay time compensation unit 24 for calculating delay times Rd1 to Rdm2 for a delay device Rd and delayed times Rc1 to Rcm1 for a delay device Rc.SELECTED DRAWING: Figure 7
【課題】制御性能の低下をある程度許容することで、制御器のゲインを小さくする。【解決手段】制御器設計装置1に備えた制御部10の同定部20は、制御対象Gp及び目標システムGtを同定し、遅延時間分離部21は、制御対象Gpから遅延時間を分離して制御対象Gp#を求め、目標システムGtから遅延時間を分離して目標システムGt#を求める。システム構成部22は、制御器H0、制御対象Gp#、目標システムGt#、減算器及びバランス係数αを用いて、全体システムHallを構成する。パラメータ決定部23は、バランス係数αを変化させ、全体システムHallのH∞ノルムを評価関数として、全体システムHallのH∞ノルムを最小化する制御器H0の係数行列A0,B0,C0,D0を決定する。遅延時間補償部24は、遅延器Rdの遅延時間Rd1〜Rdm2及び遅延器Rcの遅延時間Rc1〜Rcm1を求める。【選択図】図7</abstract><oa>free_for_read</oa></addata></record> |
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subjects | DEAF-AID SETS ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKEACOUSTIC ELECTROMECHANICAL TRANSDUCERS PUBLIC ADDRESS SYSTEMS |
title | CONTROLLER DESIGN APPARATUS FOR ACOUSTIC SIGNAL, AND PROGRAM |
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