SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

To provide an MISFET on a semiconductor substrate, which has an equal channel length all around.SOLUTION: An MISFET comprises: a pair of SiGe layers 4 (first semiconductor layers) provided on an Si substrate 1 in which a trench lies partially; a pair of SiGe layers 5 (second semiconductor layers) provided between the SiGe layers 4 and in which one lateral face contacts each SiGe layer 4; a surrounding gate electrode 9 which is provided between the SiGe layers 5 and has opposite lateral faces lying next to the SiGe layers 5 via a strained Si layer 6 (third semiconductor layer), respectively, and in which a trench where an insulation film 7 is formed on lateral faces and a bottom face is embedded all around the strained Si layer 6 via a gate insulation film 8; ntype source drain regions (10, 13) which are provided in the SiGe layers 4 and each of which has an end having a plane perpendicular to a principal surface of the Si substrate 1; n type source drain regions (11, 12) which are provided in the SiGe layers 5 and each of which has an end having a plane perpendicular to the principal surface of the Si substrate 1; and a channel region which is provided in the strained Si layer 6 and has an equal channel length all around.SELECTED DRAWING: Figure 1 【課題】全周囲等しいチャネル長を有する半導体基板上のＭＩＳＦＥＴの提供【解決手段】一部に溝（トレンチ）を有するＳｉ基板１上に一対のＳｉＧｅ層４（第１の半導体層）を設け、ＳｉＧｅ層４間に１側面をそれぞれ接して一対のＳｉＧｅ層５（第２の半導体層）を設け、ＳｉＧｅ層５間に対向する側面をそれぞれ接して歪みＳｉ層６（第３の半導体層）を挟んで設け、歪みＳｉ層６の全周囲にゲート絶縁膜８を介し、側面及び下面に絶縁膜７が形成された溝を埋め込んだ包囲型ゲート電極９を設け、ＳｉＧｅ層４には、端部がＳｉ基板１の主面に対し垂直な平面を有する、ｎ＋型ソースドレイン領域（１０、１３）を、ＳｉＧｅ層５には、端部がＳｉ基板１の主面に対し垂直な平面を有する、ｎ型ソースドレイン領域（１１、１２）をそれぞれ設け、歪みＳｉ層６には全周囲等しいチャネル長のチャネル領域を設けたＭＩＳＦＥＴ。【選択図】図１