SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a vertical power MOSFET with a super junction structure, in which, such a problem that, along with the higher aspect ratio of an n-type column region and a p-type column region, the breakdown voltage of a power MOSFET cannot be secured due to variations in impurity c...

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Bibliographische Detailangaben
Hauptverfasser: YAMAGUCHI NATSUO, ABIKO YUYA, EGUCHI SOJI
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a vertical power MOSFET with a super junction structure, in which, such a problem that, along with the higher aspect ratio of an n-type column region and a p-type column region, the breakdown voltage of a power MOSFET cannot be secured due to variations in impurity concentration of the p-type column region is prevented.SOLUTION: A p-type semiconductor region PR1 is formed on a side surface of an n-type column region NC1 adjacent to a p-type column region PC1. Here, a side surface of the entire p-type column region including the p-type semiconductor region PR1 and the p-type column region PC1 is tilted by forming the p-type semiconductor region PR1 over approximately half the depth from an upper end of the height from the upper end to a lower end of the side surface of the n-type column region NC1.SELECTED DRAWING: Figure 2 【課題】スーパージャンクション構造を採用した縦型パワーMOSFETにおいて、n型カラム領域およびp型カラム領域の高アスペクト比化に伴いp型カラム領域の不純物濃度のばらつきに起因して、パワーMOSFETの耐圧が確保できなくなることを防ぐ。【解決手段】p型カラム領域PC1と隣接するn型カラムNC1の側面に、p型半導体領域PR1を形成する。ここでは、n型カラム領域NC1の側面の上端から下端までの高さのうち、当該上端から半分程度の深さに亘ってp型半導体領域PR1を形成することで、p型半導体領域PR1とp型カラム領域PC1とを含むp型カラム領域全体の側面を傾ける。【選択図】図2