SEMICONDUCTOR DEVICE AND DATA SYNCHRONIZATION METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor device which synchronizes data synchronized to a first clock signal by a second clock signal.SOLUTION: A semiconductor device generates a first delay clock signal obtained by delaying a second clock signal for a predetermined time, and a second delay clock signal obtained by delaying the first delay clock signal for the predetermined time, and fetches first fetching data at a time when the second clock signal is transferred from a first logical value to a second logical value, and second fetch data at the time when the second delay clock signal is transferred from the first logical value to the second logical value. The semiconductor device fetches a first clock signal value (first clock value) at the time when the second clock signal is transferred from the first logical value to the second logical value, and a first clock signal value (second clock value) at the time when the first delay clock signal is transferred from the first logical value to the second logical value. When the first and second clock values are the first logical value, the data obtained by synchronizing first fetching data by the second clock signal is output. When one of or both the first and second clock values is/are the second logical value, the data obtained by synchronizing the second fetching data by the second clock signal is output.SELECTED DRAWING: Figure 2 【課題】第１クロック信号に同期したデータを第２クロック信号で同期化する半導体装置を提供する。【解決手段】第２クロック信号を所定時間遅延した第１遅延クロック信号、第１遅延クロック信号を所定時間遅延した第２遅延クロック信号を生成し、第２クロック信号が第１から第２論理値へ遷移時点の第１取込データと、第２遅延クロック信号が第１から第２論理値へ遷移時点の第２取込データを取り込む。第２クロック信号が第１から第２論理値へ遷移時点での第１クロック信号値（第１クロック値）と、第１遅延クロック信号が第１から第２論理値へ遷移時点での第１クロック信号値（第２クロック値）を取り込む。第１及び第２クロック値が共に第１の論理値の場合は第１取込データを第２クロック信号で同期化したデータを出力し、第１及び第２クロック値のうちの一方又は双方が第２の論理値の場合は第２取込データを第２クロック信号で同期化したデータを出力する。【選択図】図２