SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

PROBLEM TO BE SOLVED: To provide an MIS field effect transistor which has a surrounding gate electrode with an SOI structure.SOLUTION: A semiconductor device including an MIS field effect transistor provided on a semiconductor substrate 1 via an insulation film 2 comprises: a fully depleted semiconductor layer as an SOI substrate composed of a structure where a pair of second semiconductor layers 7 are provided to sandwich a third semiconductor layer 8 from both sides and a pair of first semiconductor layers 6 are provided to sandwich the pair of second semiconductor layers 7 from outside; a surrounding gate electrode 10 provided around the third semiconductor layer 8 via a gate oxide film 9; high-concentration source/drain regions (11, 14) which are provided in the first semiconductor layer 6 and have ends having a plane perpendicular to a principal surface of the semiconductor substrate 1; and low-concentration source/drain regions (12, 13) which are provided in the second semiconductor layer 7 and have ends having a plane perpendicular to the principal surface of the semiconductor substrate 1, in which a channel region with channel lengths equal to each other around an entire circumference is provided in the third semiconductor layer 8.SELECTED DRAWING: Figure 1 【課題】ＳＯＩ構造の包囲型ゲート電極を有するＭＩＳ電界効果トランジスタの提供【解決手段】第３の半導体層８を左右から挟んだ一対の第２の半導体層７を設け、さらに一対の第２の半導体層７をそれぞれ外側から挟んだ一対の第１の半導体層６を設けた構造からなる完全空乏型の半導体層をＳＯＩ基板とし、第３の半導体層８の周囲にゲート酸化膜９を介して包囲型ゲート電極１０を設け、第１の半導体層６に端部が半導体基板１の主面に対し、垂直な平面を有する高濃度のソースドレイン領域（１１、１４）を設け、第２の半導体層７に端部が半導体基板１の主面に対し、垂直な平面を有する低濃度のソースドレイン領域（１２、１３）を設け、第３の半導体層８に全周囲のチャネル長が等しいチャネル領域を設けたＳＯＩ構造のＭＩＳ電界効果トランジスタを半導体基板１上に絶縁膜２を介して設けたものである。【選択図】図１