RECEIVING CIRCUIT, RECEIVING DEVICE, AND RECEIVING METHOD

PROBLEM TO BE SOLVED: To allow the timing of received data to be adjusted simply and accurately.SOLUTION: A receiving circuit includes: a delay element 103 for dividing received data into plural pieces of division data, and gives different amounts of delay to the respective pieces of division data;...

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1. Verfasser: TAKADA ISAO
Format: Patent
Sprache:eng ; jpn
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Zusammenfassung:PROBLEM TO BE SOLVED: To allow the timing of received data to be adjusted simply and accurately.SOLUTION: A receiving circuit includes: a delay element 103 for dividing received data into plural pieces of division data, and gives different amounts of delay to the respective pieces of division data; a plurality of flip-flops FF 104 for extracting the plural pieces of division data delayed by the delay element 103 at a moment of a common clock CLK and outputting obtained data; and a bit slip detection/selector unit 115 for identifying a flip-flop FF 104 about which a bit slip has occurred in a data signal on the basis of data signals output by the plurality of FF 104, and selecting data output by a flip-flop FF 104 with a different amount of delay from the identified FF 104 as data for reproduction of the reception data.SELECTED DRAWING: Figure 1 【課題】受信したデータを簡単かつ精度良くタイミング調整できること。【解決手段】受信したデータを複数に分配し、分配した複数のデータのそれぞれに異なる遅延量を与える遅延素子103と、遅延素子103で遅延させた複数のデータを共通のクロックCLKで打ち抜き、打ち抜かれたデータをそれぞれ出力する複数のFF104と、複数のFF104が出力するデータ信号に基づき、データ信号にビットスリップが生じたFF104を特定し、特定したFF104と異なる遅延量のFF104が出力するデータを受信データの再生用として選択するビットスリップ検出/セレクタ部115と、を備える。【選択図】図1