WIRING STRUCTURE, PRINTED BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING STRUCTURE
PROBLEM TO BE SOLVED: To provide a wiring structure capable of increasing a current capacity of a wiring pattern whose current amount is large without preventing miniaturization of a signal line and the like nor increasing a film thickness.SOLUTION: A wiring structure comprises a resin layer 1, and...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; jpn |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | CHIKAI TOMOYA IWASAKI TOSHIHIRO HAYASHI NAOKI MATSUBARA HIROAKI |
| description | PROBLEM TO BE SOLVED: To provide a wiring structure capable of increasing a current capacity of a wiring pattern whose current amount is large without preventing miniaturization of a signal line and the like nor increasing a film thickness.SOLUTION: A wiring structure comprises a resin layer 1, and wiring 3 formed on the resin layer 1. The resin layer 1 has a plurality of parallel grooves 2 in a region where the wiring is formed. The wiring 3 consists of a plating film formed on a resin layer surface 1a in a region where the wiring is formed and on an inner wall surface 1b of the plurality of grooves.SELECTED DRAWING: Figure 1
【課題】信号線などの微細化を妨げることなく、また、膜厚を増大させることなく電流量の多い配線パターンの電流容量を増大させた配線構造を提供すること。【解決手段】樹脂層１と、前記樹脂層１に形成された配線３と、を備え、前記樹脂層１は配線が形成される領域内に複数の平行な溝２を有しており、前記配線３は、前記配線が形成される領域内の樹脂層表面１ａと前記複数の溝の内壁面１ｂとに形成されたメッキ膜からなっている配線構造。【選択図】図１ |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2017162895A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2017162895A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2017162895A3</originalsourceid><addsrcrecordid>eNrjZEgO9wzy9HNXCA4JCnUOCQ1y1VEIAAqEuLooOPk7BrnoKAS7-no6-_u5AKX9gxRcXMM8nYGKHP1cFHxdQzz8XRT83RR8Hf1C3RxB-kFmoRvJw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDAzNDc2MLCxNHY2JUgQAoM41AA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIRING STRUCTURE, PRINTED BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING STRUCTURE</title><source>esp@cenet</source><creator>CHIKAI TOMOYA ; IWASAKI TOSHIHIRO ; HAYASHI NAOKI ; MATSUBARA HIROAKI</creator><creatorcontrib>CHIKAI TOMOYA ; IWASAKI TOSHIHIRO ; HAYASHI NAOKI ; MATSUBARA HIROAKI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a wiring structure capable of increasing a current capacity of a wiring pattern whose current amount is large without preventing miniaturization of a signal line and the like nor increasing a film thickness.SOLUTION: A wiring structure comprises a resin layer 1, and wiring 3 formed on the resin layer 1. The resin layer 1 has a plurality of parallel grooves 2 in a region where the wiring is formed. The wiring 3 consists of a plating film formed on a resin layer surface 1a in a region where the wiring is formed and on an inner wall surface 1b of the plurality of grooves.SELECTED DRAWING: Figure 1
【課題】信号線などの微細化を妨げることなく、また、膜厚を増大させることなく電流量の多い配線パターンの電流容量を増大させた配線構造を提供すること。【解決手段】樹脂層１と、前記樹脂層１に形成された配線３と、を備え、前記樹脂層１は配線が形成される領域内に複数の平行な溝２を有しており、前記配線３は、前記配線が形成される領域内の樹脂層表面１ａと前記複数の溝の内壁面１ｂとに形成されたメッキ膜からなっている配線構造。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170914&DB=EPODOC&CC=JP&NR=2017162895A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170914&DB=EPODOC&CC=JP&NR=2017162895A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHIKAI TOMOYA</creatorcontrib><creatorcontrib>IWASAKI TOSHIHIRO</creatorcontrib><creatorcontrib>HAYASHI NAOKI</creatorcontrib><creatorcontrib>MATSUBARA HIROAKI</creatorcontrib><title>WIRING STRUCTURE, PRINTED BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING STRUCTURE</title><description>PROBLEM TO BE SOLVED: To provide a wiring structure capable of increasing a current capacity of a wiring pattern whose current amount is large without preventing miniaturization of a signal line and the like nor increasing a film thickness.SOLUTION: A wiring structure comprises a resin layer 1, and wiring 3 formed on the resin layer 1. The resin layer 1 has a plurality of parallel grooves 2 in a region where the wiring is formed. The wiring 3 consists of a plating film formed on a resin layer surface 1a in a region where the wiring is formed and on an inner wall surface 1b of the plurality of grooves.SELECTED DRAWING: Figure 1
【課題】信号線などの微細化を妨げることなく、また、膜厚を増大させることなく電流量の多い配線パターンの電流容量を増大させた配線構造を提供すること。【解決手段】樹脂層１と、前記樹脂層１に形成された配線３と、を備え、前記樹脂層１は配線が形成される領域内に複数の平行な溝２を有しており、前記配線３は、前記配線が形成される領域内の樹脂層表面１ａと前記複数の溝の内壁面１ｂとに形成されたメッキ膜からなっている配線構造。【選択図】図１</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEgO9wzy9HNXCA4JCnUOCQ1y1VEIAAqEuLooOPk7BrnoKAS7-no6-_u5AKX9gxRcXMM8nYGKHP1cFHxdQzz8XRT83RR8Hf1C3RxB-kFmoRvJw8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDAzNDc2MLCxNHY2JUgQAoM41AA</recordid><startdate>20170914</startdate><enddate>20170914</enddate><creator>CHIKAI TOMOYA</creator><creator>IWASAKI TOSHIHIRO</creator><creator>HAYASHI NAOKI</creator><creator>MATSUBARA HIROAKI</creator><scope>EVB</scope></search><sort><creationdate>20170914</creationdate><title>WIRING STRUCTURE, PRINTED BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING STRUCTURE</title><author>CHIKAI TOMOYA ; IWASAKI TOSHIHIRO ; HAYASHI NAOKI ; MATSUBARA HIROAKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2017162895A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHIKAI TOMOYA</creatorcontrib><creatorcontrib>IWASAKI TOSHIHIRO</creatorcontrib><creatorcontrib>HAYASHI NAOKI</creatorcontrib><creatorcontrib>MATSUBARA HIROAKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHIKAI TOMOYA</au><au>IWASAKI TOSHIHIRO</au><au>HAYASHI NAOKI</au><au>MATSUBARA HIROAKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIRING STRUCTURE, PRINTED BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING STRUCTURE</title><date>2017-09-14</date><risdate>2017</risdate><abstract>PROBLEM TO BE SOLVED: To provide a wiring structure capable of increasing a current capacity of a wiring pattern whose current amount is large without preventing miniaturization of a signal line and the like nor increasing a film thickness.SOLUTION: A wiring structure comprises a resin layer 1, and wiring 3 formed on the resin layer 1. The resin layer 1 has a plurality of parallel grooves 2 in a region where the wiring is formed. The wiring 3 consists of a plating film formed on a resin layer surface 1a in a region where the wiring is formed and on an inner wall surface 1b of the plurality of grooves.SELECTED DRAWING: Figure 1
【課題】信号線などの微細化を妨げることなく、また、膜厚を増大させることなく電流量の多い配線パターンの電流容量を増大させた配線構造を提供すること。【解決手段】樹脂層１と、前記樹脂層１に形成された配線３と、を備え、前記樹脂層１は配線が形成される領域内に複数の平行な溝２を有しており、前記配線３は、前記配線が形成される領域内の樹脂層表面１ａと前記複数の溝の内壁面１ｂとに形成されたメッキ膜からなっている配線構造。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; jpn |
| recordid | cdi_epo_espacenet_JP2017162895A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | WIRING STRUCTURE, PRINTED BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING STRUCTURE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T04%3A01%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHIKAI%20TOMOYA&rft.date=2017-09-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2017162895A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |