WIRING STRUCTURE, PRINTED BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING STRUCTURE
PROBLEM TO BE SOLVED: To provide a wiring structure capable of increasing a current capacity of a wiring pattern whose current amount is large without preventing miniaturization of a signal line and the like nor increasing a film thickness.SOLUTION: A wiring structure comprises a resin layer 1, and...
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Format: | Patent |
Sprache: | eng ; jpn |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a wiring structure capable of increasing a current capacity of a wiring pattern whose current amount is large without preventing miniaturization of a signal line and the like nor increasing a film thickness.SOLUTION: A wiring structure comprises a resin layer 1, and wiring 3 formed on the resin layer 1. The resin layer 1 has a plurality of parallel grooves 2 in a region where the wiring is formed. The wiring 3 consists of a plating film formed on a resin layer surface 1a in a region where the wiring is formed and on an inner wall surface 1b of the plurality of grooves.SELECTED DRAWING: Figure 1
【課題】信号線などの微細化を妨げることなく、また、膜厚を増大させることなく電流量の多い配線パターンの電流容量を増大させた配線構造を提供すること。【解決手段】樹脂層1と、前記樹脂層1に形成された配線3と、を備え、前記樹脂層1は配線が形成される領域内に複数の平行な溝2を有しており、前記配線3は、前記配線が形成される領域内の樹脂層表面1aと前記複数の溝の内壁面1bとに形成されたメッキ膜からなっている配線構造。【選択図】図1 |
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